PLO device

An optical receiving device for receiving an optical signal, comprising:

• a photoelectric conversion section for converting the optical signal to an electrical signal;
• a Phase Locked Oscillator (PLO) section including a first voltage detection section having a shifted data generation part for shifting input data, which is the electrical signal, with use of recovered clock to generate shifted data, a first phase comparison part for comparing phases of the input data and the shifted data with each other and outputting first difference data, and a first filter for removing an alternating-current component from the first difference data and outputting a first detection voltage;
• a second voltage detection section having a delay part for delaying the input data for a time corresponding to half of one time slot with use of an analog delay element and outputting delayed data, a second phase comparison part for comparing phases of the input data and the delayed data with each other and outputting second difference data, and a second filter for removing an alternating-current component from the second difference data and outputting a second detection voltage;
• an arithmetic section for dividing the first detection voltage by the second detection voltage to obtain a control voltage;
• and a clock oscillation section for outputting the recovered clock with an oscillation frequency thereof varied in accordance with the control voltage;
• and
• an identification/recovery section for identifying and recovering data information in the electrical signal in accordance with the recovered clock.

A clock data recovery device for extracting clock, which is timing information, from input data to recover data, comprising:

• a Phase Locked Oscillator (PLO) including a first voltage detection section having a shifted data generation part for shifting the input data with use of recovered clock to generate shifted data, a first phase comparison part for comparing phases of the input data and the shifted data with each other and outputting first difference data, and a first filter for removing an alternating-current component from the first difference data and outputting a first detection voltage;
• a second voltage detection section having a delay part for delaying the input data for a time corresponding to half of one time slot with use of an analog delay element and outputting delayed data, a second phase comparison part for comparing phases of the input data and the delayed data with each other and outputting second difference data, and a second filter for removing an alternating-current component from the second difference data and outputting a second detection voltage;
• an arithmetic section for dividing the first detection voltage by the second detection voltage to obtain a control voltage;
• and a clock oscillation section for outputting the recovered clock with an oscillation frequency thereof varied in accordance with the control voltage;
• and
• an identification/recovery section for identifying and recovering the input data in accordance with the recovered clock.

A Formed Error Correction (FEC) for performing an error correction process for input data, comprising:

• a clock data recovery section including a Phase Locked Oscillator (PLO) section and an identification/recovery section,
• the PLO section including a first voltage detection section having a shifted data generation part for shifting the input data with use of recovered clock to generate shifted data, a first phase comparison part for comparing phases of the input data and the shifted data with each other and outputting first difference data, and a first filter for removing an alternating-current component from the first difference data and outputting a first detection voltage;
• a second voltage detection section having a delay part for delaying the input data for a time corresponding to half of one time slot with use of an analog delay element and outputting delayed data, a second phase comparison part for comparing phases of the input data and the delayed data with each other and outputting second difference data, and a second filter for removing an alternating-current component from the second difference data and outputting a second detection voltage;
• an arithmetic section for dividing the first detection voltage by the second detection voltage to obtain a control voltage;
• and a clock oscillation section for outputting the recovered clock with an oscillation frequency thereof varied in accordance with the control voltage,
• the identification/recovery section identifying and recovering the input data in accordance with the recovered clock;
• and
• an FEC section for performing a process of correcting errors in the identified/recovered data.

A phase lock loop method for performing clock recovery based on an input signal, comprising:

• shifting input data with use of recovered clock to generate shifted data;
• comparing phases of the input data and the shifted data with each other and outputting first difference data;
• removing an alternating-current component from the first difference data to obtain a first detection voltage containing parameters related to phase difference, transition rate and Signal Noise Ratio (S/N);
• delaying the input data for a time corresponding to half of one time slot with use of an analog delay element to obtain delayed data;
• comparing phases of the input data and the delayed data with each other and outputting second difference data;
• removing an alternating-current component from the second difference data to obtain a second detection voltage containing the parameters related to transition rate and S/N;
• dividing the first detection voltage by the second detection voltage to obtain a control voltage free of the parameters related to transition rate and S/N;
• and
• generating the recovered clock with an oscillation frequency varied in accordance with the control voltage which is independent of the parameters related to transition rate and S/N.