Wireless communication apparatus processing intermittent data
AssigneeHitachi, Ltd.
InventorsTakashi Yano, May Suzuki
Life of this patent
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Abstract
In order to effectively reduce power consumption of a terminal in a wireless communication apparatus upon packet communication, the wireless communication apparatus has a plurality of signal processing blocks having different signal processing periods; a buffer memory which links the signal processing blocks; and a clock control part which supplies or suspends a clock signal to each block. Each of the signal processing blocks watches whether or not there is data to be processed in the subsequent signal processing block. Based on the watched result, the clock control part controls an operation to supply or suspend the clock signal to the subsequent signal processing block.
Claims8
A wireless communication apparatus having a wireless processing part for processing a wireless signal including intermittent data and a base band signal processing part for receiving/transmitting said intermittent data to/from said wireless processing part, wherein said base band signal processing part comprises:
- a plurality of signal processing blocks having different signal processing periods;
- a buffer memory which is provided between said plurality of signal processing blocks;
- a clock control part which supplies a clock signal to each of said plurality of signal processing blocks and said buffer memory;
- a power source control part which supplies a power source to each of said plurality of signal processing parts and said buffer memory;
- and
- a control engine which controls said plurality of signal processing blocks, said buffer memory, said clock control part, and said power source control part, and
- at least one of said plurality of signal processing blocks has means for watching which watches whether or not there is data to be processed in the subsequent signal processing block having the different signal processing period, and
- said control engine also controls said clock control part to supply or suspend the clock signal to said subsequent signal processing block based on a watched result of said means for watching.
A large scale integrated circuit comprising:
- a plurality of signal processing blocks having different signal processing periods;
- a buffer memory which is provided between said plurality of signal processing blocks;
- a clock control part which supplies a clock signal to each of said plurality of signal processing blocks and said buffer memory;
- a power source control part which supplies a power source to each of said plurality of signal processing blocks and said buffer memory;
- and
- a control engine which controls said plurality of signal processing blocks, said buffer memory, said clock control part, and said power source control part, wherein
- at least one of said plurality of signal processing blocks has means for watching which watches whether or not there is data to be processed in the subsequent signal processing block having the different processing period, and said control engine has means for controlling said clock control part to supply or suspend the clock signal to said subsequent signal processing block based on a watched result of said means for watching.
Dependencies are inferred from the claim text.