Circuit and method for self trimming frequency acquisition

A method of self-trimming a voltage controlled oscillator (VCO) for frequency acquisition comprising:

• providing a loop network having a frequency detector;
• receiving a frequency stream at said frequency detector;
• comparing an averaged output from said frequency detector and generating a logic bit in response to said comparison;
• registering at a shift register said logic bit;
• controlling a frequency of the VCO via a ramp generator coupled to the VCO;
• and
• generating a stop pulse in response to an event occurring at said shift register, the event solely including a detected transition between a series of consecutive positive outputs and a series of consecutive negative outputs from the frequency detector that is indicative of a center frequency, said stop pulse received at said ramp generator.

A clock and data recover CDR circuit for frequency acquisition of an incoming data signal, the circuit comprising:

• a phase loop having a phase detector, said phase loop being configured to lock a phase of the incoming data signal;
• a frequency loop having a frequency detector coupled to said phase loop and to a voltage controlled oscillator (VCO) having a frequency, said frequency loop configured to change the frequency of the VCO and to receive the incoming data signal;
• and
• a trimming loop coupled to said frequency detector and configured to sweep the frequency of said VCO and to trim a frequency range of said VCO,
• wherein said trimming loop includes a decision circuit and a RAM generator coupled to said decision circuit,
• wherein said decision circuit includes:
• a shift register to hold at least a number of samples corresponding to two steps with ten samples for each step;
• and
• a logic design coupled to said shift register configured to send a stop pulse to said ramp generator.

A clock and data recovery (CDR) circuit for frequency acquisition of an incoming data signal, the circuit comprising:

• a phase loop having a phase detector, said phase loop being configured to lock a phase of the incoming data signal;
• a frequency loop having a frequency detector coupled to said phase loop and to a voltage controlled oscillator (VCO) having a frequency, said frequency loop configured to change the frequency of the VCO and to receive the incoming data signal;
• and
• a trimming loop coupled to said frequency detector and configured to sweep the frequency of said VCO and to trim a frequency range of said VCO,
• wherein said trimming loop includes a ramp generator to provide a bias current to said VCO,
• wherein said VCO comprises a ring oscillator and said ramp generator comprises a digital counter and a decoder, said ramp generator configured to increase the frequency of said VCO by increasing the bias current of said VCO.

A clock and data recovery (CDR) circuit for frequency acquisition of an incoming data signal, the circuit comprising:

• a phase loop having a phase detector, said phase loop being configured to lock a phase of the incoming data signal;
• a frequency loop having a frequency detector coupled to said phase loop and to a voltage controlled oscillator (VCO) having a frequency, said frequency loop configured to change the frequency of the VCO and to receive the incoming data signal;
• and
• a trimming loop coupled to said frequency detector and configured to sweep the frequency of said VCO and to trim a frequency range of said VCO,
• further comprising a frequency window configuration to compare a beat frequency of the incoming data and a beat frequency of the VCO, said frequency window configuration operative to signal a switch coupled to the VCO to engage said frequency loop and said phase loop if said beat frequencies near an acceptable difference.