System and method for asynchronous switching of composite cells, and corresponsing input port and output port modules

An input port module for use in a system for asynchronously switching cells each comprising a header field and a data field, of the type interconnecting incoming links and outgoing links, each of said links multiplexing data belonging to at least two synchronous channels, said system comprising input port modules and output port modules interconnected by at least one stage of intermediate switching elements,

• each input module comprising composite cell forming means comprising:
• means for memorizing channel data received on incoming channels over incoming links of the input port module;
• means for constructing channel data blocks each channel data block comprising channel data to be transmitted which are extracted from the channel data received and at least one explicit channel identifier associated with said channel data to be transmitted, and
• means for selectively multiplexing channel data blocks of different channels intended for a common destination corresponding to at least one same destination output port module, in the data field of at least one composite cell to be transmitted to said common destination,
• wherein said explicit channel identifier explicitly designater the address of an incoming synchronous channel in an input port module, or the address of at least one outgoing synchronous channel in an output port module.

An output port module for a system for asynchronously switching cells each comprising a header field and a data field, which system is of the type interconnecting incoming links and outgoing links, each of said links multiplexing data belonging to at least two synchronous channels, said system comprising input port modules and output port modules interconnected by at least one stage of intermediate switching elements, each output module comprising means for processing said composite cells, comprising:

• means for extracting and recognizing said received channel data blocks in the data field of a composite cell by means of said associated explicit channel identifiers, and
• means for transmitting to at least one outgoing link the channel data belonging to the various channels, as a function of said associated explicit channel identifiers,
• wherein said explicit channel identifier explicitly designates
• the address of an incoming synchronous channel in an input port module,
• or the address of at least one outgoing synchronous channel in an output port module.

A method of asynchronously switching cells each comprising a header field and a data field, using a system interconnecting incoming links and outgoing links, each of said links multiplexing data belonging to at least two synchronous channels, said system comprising input port modules and output port modules interconnected by at least one stage of switching elements,

• comprises the following steps:
• forming composite cells in at least one of said input modules, comprising the steps of:
• memorizing channel data received on incoming channels over incoming links of the input port module;
• constructing channel data blocks each channel data block comprising channel data to be transmitted which are extracted from the channel data received and at least one explicit channel identifier associated with said channel data to be transmitted, and
• selectively multiplexing channel data blocks of different channels intended for a common destination corresponding to at least one same destination output port module, in the data field of at least one composite cell to be transmitted to said common destination, and
• processing said composite cells in at least one of said output modules, including the steps of:
• extracting and recognizing said received channel data blocks in the data field of a composite cell by means of said associated explicit channel identifier, and
• transmitting to at least one outgoing link the channel data belonging to the various channels, as a function of said associated explicit channel identifier,
• wherein said explicit channel identifier explicitly designates the address of an incoming synchronous channel in an input port module, or the address of at least one outgoing synchronous channel in an output port module.