Circuit and method for reading data transfers that are sent with a source synchronous clock signal
AssigneeInternational Business Machines Corporation
InventorsPaul W. Coteus, Frank D. Ferraiolo, Kevin C. Gower
Life of this patent
Estimating the term…
Abstract
A circuit and method for reading data transfers that are sent with a source synchronous clock signal. The circuit has a data input for receiving data signals carrying data being transferred, a clock input for receiving synchronous clock signals, and a delay circuit connected to the clock input for generating a delayed clock signal which is delayed from said synchronous clock signal a predetermined time period. The circuit also includes a pipeline connected to the data input for sampling the data on the data input in response to said delayed clock signal thereby stretching the sampling of incoming data.
Claims8
A circuit for reading data transfers that are sent with a source synchronous clock signal, said circuit comprising:
- a data input for receiving data signals carrying data being transferred;
- a clock input for receiving synchronous clock signals;
- a delay circuit connected to said clock input for generating a delayed clock signal which is delayed from said synchronous clock signal a predetermined time period;
- and
- a pipeline connected to said data input for sampling the data on said data input in response to said delayed clock signal thereby stretching the sampling of incoming data;
- said delay circuit comprising:
- a read clock providing a read clock signal having a frequency delayed from said synchronous clock signal to time all possible arrivals of stretched, incoming data, and
- a local clock providing a local clock signal having a programmed frequency selected to define a local time domain;
- said pipeline comprising:
- a read latch clocked by said read clock signal for latching data bits from said data input, and
- a local latch clocked by said local clock signal for latching data bits from said read latch within said local time domain;
- and
- a selection device selecting the output of one of said read latch or said local latch.
A method for reading data transfers that are sent with a source synchronous clock signal, said method comprising:
- receiving at a data input, data signals carrying data being transferred;
- receiving at a clock input, synchronous clock signals;
- generating a delayed clock signal which is delayed from said synchronous clock signal a predetermined time period;
- sampling in a pipeline, the data on said data input in response to said delayed clock signal thereby stretching the sampling of incoming data;
- delaying a read clock having a frequency delayed from said synchronous clock signal to time all possible arrivals of stretched, incoming data;
- clocking a read latch in said pipeline by said read clock, thereby capturing all possible arrivals of stretched, incoming data;
- programming a local clock signal having a programmed frequency selected to define a local time domain;
- clocking a local latch in said pipeline by said local clock signal, thereby capturing latched data of said read latch within said local time domain;
- and
- selecting the output of one of said read latch or said local latch.
Dependencies are inferred from the claim text.