Back to results
US 6,807,119 B2Granted
Array containing charge storage and dummy transistors and method of operating the array
AssigneeMatrix Semiconductor, Inc.
InventorsLuca Fasoli, Alper Ilkbahar, Roy Scheuerlein
Life of this patent
Estimating the term…
Abstract
An array of transistors includes a plurality of charge storage transistors and a plurality of dummy transistors interspersed with the plurality of charge storage transistors. Each of the plurality of the dummy transistors is made using the same photolithographic masking steps as each of the plurality of the charge storage transistors. A method of operating the array includes programming and/or erasing the array of transistors, and reading the plurality of charge storage transistors but not the plurality of dummy transistors.
Claims43
A method of operating an array of transistors, comprising:
- (a) providing the array of transistors, comprising:
- a plurality of charge storage transistors;
- and
- a plurality of dummy transistors interspersed with the plurality of charge storage transistors;
- wherein each of the plurality of the dummy transistors is made using same photolithographic masking steps as each of the plurality of the charge storage transistors;
- (b) performing at least one of programming and erasing the array of transistors;
- and
- (c) reading the plurality of charge storage transistors but not the plurality of dummy transistors of the array of transistors.
5 more elements
A semiconductor device, comprising:
- (a) an array of transistors comprising:
- (i) a plurality of charge storage transistors;
- and
- (ii) a plurality of dummy transistors interspersed with the plurality of charge storage transistors, wherein each of the plurality of the dummy transistors is made using same photolithographic masking steps as each of the plurality of the charge storage transistors;
- and
- (b) a first means for:
- (i) performing at least one of programming and erasing the array of transistors;
- and
- (ii) reading the plurality of charge storage transistors but not the plurality of dummy transistors of the array of transistors.
6 more elements
A semiconductor device, comprising:
- (a) an array of transistors, comprising:
- (i) a plurality of charge storage transistors;
- and
- (ii) a plurality of dummy transistors interspersed with the plurality of charge storage transistors, wherein each of the plurality of the dummy transistors is made using same photolithographic masking steps as each of the plurality of the charge storage transistors;
- and
- (b) peripheral programming circuitry operable to:
- (i) program or erase the array of transistors;
- and
- (ii) read the plurality of charge storage transistors but not the plurality of dummy transistors of the array of transistors.
6 more elements
A method of biasing an array of transistors, comprising:
- (a) providing the array of transistors comprising a plurality of charge storage transistors and a plurality of dummy transistors interspersed with the plurality of charge storage transistors, wherein each of the plurality of the dummy transistors is made using same photolithographic masking steps as each of the plurality of the charge storage transistors;
- and
- (b) reading each selected charge storage transistor of the plurality of charge storage transistors, wherein the step of reading each selected charge storage transistor comprises:
- applying a gate read voltage to a selected word line of the selected charge storage transistor, wherein the gate read voltage is lower than a programming voltage;
- applying a drain read voltage to a selected drain bit line of the selected charge storage transistor;
- applying a source read voltage to a selected source bit line of the selected charge storage transistor, wherein the source read voltage is different than the drain read voltage;
- grounding or biasing unselected word lines to a reference voltage, wherein the reference voltage is lower than a programming voltage;
- reading the selected charge storage transistor by measuring a current on the selected source bit line or the selected drain bit line of the selected charge storage transistor;
- prior to the step of reading the selected charge storage transistor,
- (i) precharging at least one unselected bit line located adjacent to the selected source bit line of the selected charge storage transistor to the source read voltage if the selected charge storage transistor is read by measuring the current on the selected source bit line;
- or
- (ii) precharging at least one unselected bit line located adjacent to the selected drain bit line of the selected charge storage transistor to the drain read voltage if the selected charge storage transistor is read by measuring the current on the selected drain bit line;
- and
- during the step of reading the selected charge storage transistor,
- (i) allowing the at least one unselected precharged bit line to float;
- or
- (ii) maintaining the at least one unselected precharged bit line at the source or drain read voltage;
- wherein the plurality of dummy transistors are not read during the step of reading each selected charge storage transistor.
15 more elements
Dependencies are inferred from the claim text.