Adjustable offset differential amplifier

A resistive cross-point memory cell sensor comprising:

• an adjustable offset differential amplifier, the adjustable offset differential amplifier comprising:
• a first differential circuit receiving a sensed signal that represents a signal of a sensed resistive cross-point memory cell;
• a second differential circuit receiving a reference input;
• a differential amplifier output having an amplitude proportional to a difference between the sensed signal and the reference input;
• the first differential circuit comprising;
• a plurality of sub first differential transistors, gates of the sub first differential transistors receiving the sensed signal, each sub first differential transistor having an adjustable back gate bias, each of the plurality of sub first differential transistors providing a different offset adjustment sensitivity;
• control circuitry connected to the adjustable back gate bias of each of the sub first differential transistors for reducing offset errors of the differential amplifier output.

A resistive cross-point memory apparatus comprising:

• a resistive cross-point memory cell;
• an adjustable offset differential amplifier, the adjustable offset differential amplifier comprising:
• a first differential circuit receiving a sensed signal that represents a signal of a sensed resistive cross-point memory cell;
• a second differential circuit receiving a reference input;
• a differential amplifier output having an amplitude proportional to a difference between the sensed signal and the reference input;
• the first differential circuit comprising;
• a plurality of sub first differential transistors, gates of the sub first differential transistors receiving the sensed signal, each sub first differential transistor having an adjustable back gate bias, each of the plurality of sub first differential transistors providing a different offset adjustment sensitivity;
• control circuitry connected to the adjustable back gate bias of each of the sub first differential transistors for reducing offset errors of the differential amplifier output.

A resistive cross-point memory system comprising:

• an array of cross-point memory cells;
• a plurality of resistive cross-point memory cell sensors that can be electrically connected to each of the cross-point memory cells;
• each resistive cross-point memory cell sensor comprising:
• an adjustable offset differential amplifier, the adjustable offset differential amplifier comprising:
• a first differential circuit receiving a sensed signal that represents a signal of a sensed resistive cross-point memory cell;
• a second differential circuit receiving a reference input;
• a differential amplifier output having an amplitude proportional to a difference between the sensed signal and the reference input;
• the first differential circuit comprising;
• a plurality of sub first differential transistors, gates of the sub first differential transistors receiving the sensed signal, each sub first differential transistor having an adjustable back gate bias, each of the plurality of sub first differential transistors providing a different offset adjustment sensitivity;
• control circuitry connected to the adjustable back gate bias of each of the sub first differential transistors for reducing offset errors of the differential amplifier output.

A computer system comprising:

• a central processing unit;
• an array of cross-point memory cells, the array of cross-point memory cells that the central processing unit can store and access data, the array of cross-point memory cells comprising;
• a plurality of resistive cross-point memory cell sensors that can be electrically connected to each of the cross-point memory cells;
• each resistive cross-point memory cell sensor comprising:
• an adjustable offset differential amplifier, the adjustable offset differential amplifier comprising:
• a first differential circuit receiving a sensed signal that represents a signal of a sensed resistive cross-point memory cell;
• a second differential circuit receiving a reference input;
• a differential amplifier output having an amplitude proportional to a difference between the sensed signal and the reference input;
• the first differential circuit comprising;
• a plurality of sub first differential transistors, gates of the sub first differential transistors receiving the sensed signal, each sub first differential transistor having an adjustable back gate bias, each of the plurality of sub first differential transistors providing a different offset adjustment sensitivity;
• control circuitry connected to the adjustable back gate bias of each of the sub first differential transistors for reducing offset errors of the differential amplifier output.

A method for reducing offset errors of a differential amplifier, comprising:

• adjusting a coarse offset adjustment of the differential amplifier by adjusting a bask gate bias of a first differential amplifier transistor;
• adjusting a fine offset adjustment of the differential amplifier by adjusting a back gate bias of a second differential amplifier transistor;
• adjusting a very fine offset adjustment of the differential amplifier by adjusting a back gate bias of a third differential amplifier transistor;
• sensing an output current of the differential amplifier;
• and
• if the sensed output current is not within a predetermined range, repeating the adjusting of the very fine offset adjustment.