Semiconductor circuit device capable of accurately testing embedded memory
AssigneeRenesas Technology Corp.
InventorsAkira Yamazaki, Atsuo Mangyo
Life of this patent
Estimating the term…
Abstract
A test clock signal for determining timing of transferring a signal to an embedded memory, a memory clock signal for determining timing of latching signal/data of the embedded memory, and a latch timing signal for sampling a signal read from the memory are selectively sampled in accordance with a correcting test clock signal by a common flip flop. The phase differences of the latch timing signal, test clock signal and memory clock signal are measured externally. Thus, it is possible to accurately measure timing conditions such as set up/hold time and access time of the embedded synchronous memory.
Claims12
A semiconductor circuit device comprising:
- a memory core operating synchronously with a memory dock signal;
- a memory transferring circuit transferring at least a signal to said memory core synchronously with a test clock signal;
- a timing selecting circuit receiving at least said memory clock signal and test clock signal, and selecting one of at least said memory clock signal and said test clock signal;
- and
- a timing transferring circuit for taking in and transferring externally an output signal of said timing selecting circuit synchronously with a correcting test clock signal.
A semiconductor circuit device comprising:
- a memory core taking in received data synchronously with a memory clock signal;
- a memory transferring circuit for transferring multi-bit data to said memory core;
- a replica circuit having a transfer characteristic identical to said memory transferring circuit and simulating operation of said memory transferring circuit;
- a test data selecting circuit selecting one of the memory clock signal and an output signal of said replica circuit;
- and
- a test data transferring circuit for transferring an output signal of said test data selecting circuit synchronously with a correcting test clock signal.
A semiconductor circuit device comprising:
- a memory core operating synchronously with a memory clock signal;
- a latch transferring circuit for taking in a signal transferred from said memory core synchronously with a latch timing signal, and transferring a latched signal externally;
- and
- a test transferring circuit for selecting one of the memory clock signal and the latch timing signal in accordance with a selection signal, and externally transferring the signal selected, synchronously with a correcting clock signal.
Dependencies are inferred from the claim text.