Method and system for selecting redundant rows and columns of memory cells

A system for selecting redundant columns of memory cells, comprising

• a programmable circuit comprising a first circuit that may be programmed to output a first defective column address corresponding to a first defective column of memory cells, and a second circuit that may be programmed to output a second defective column address corresponding to a second defective column of memory cells;
• a defective column decoder coupled to receive the first and second defective column addresses from the programmable circuit, the defective column decoder being operable to output a first shift control signal corresponding to the first defective column address and to a first shift direction, and a second shift control signal corresponding to the second defective column address and a second shift direction that is opposite the first shift direction;
• and
• a column select steering circuit coupled to receive the first and second shift control signals from the defective column decoder, the column select steering circuit being operable responsive to the first shift control signal to shift in the direction indicated by the first shift control signal the select signal for the first defective column to an adjacent column of memory cells, to shift in the first direction the select signal for one of the columns to a first redundant column of memory cells, to shift in the first direction respective select signals for the columns intermediate the first defective column and the first redundant column to respective adjacent columns of memory cells, and wherein the select signal steering circuit is further operable responsive to the second shift control signal to shift in the second direction the select signal for the second defective column to an adjacent column of memory cells, to shift in the second direction the select signal for one of the columns to a second redundant set of memory cells, and to shift in the second direction respective select signals for the columns intermediate the second defective column and the second redundant column to respective adjacent sets of memory cells.

In a memory device, a system for selecting redundant columns of memory cells, comprising:

• first means for outputting first and second defective column addresses corresponding to respective first and second defective column of memory cells;
• second means for outputting a first shift control signal corresponding to the first defective column address and to a first shift direction, and for outputting a second shift control signal corresponding to the second defective column address and a second shift direction that is opposite the first shift direction;
• third means responsive to the first shift control signal for shifting in the direction indicated by the first shift control signal the select signal for the first defective column to an adjacent column of memory cells, for shifting in the first direction the select signal for one of the columns to a first redundant column of memory cells, for shifting in the first direction respective select signals for the columns intermediate the first defective column and the first redundant column to respective adjacent columns of memory cells;
• and
• fourth means responsive to the second shift control signal for shifting in the second direction the select signal for the second defective column to an adjacent column of memory cells, for shifting in the second direction the select signal for one of the columns to a second redundant set of memory cells, and for shifting in the second direction respective select signals for the columns intermediate the second defective column and the second redundant column to respective adjacent sets of memory cells.

A memory device, comprising:

• a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
• a column address circuit operable to receive and decode column address signals applied to the external address terminals;
• an array of memory cells operable to store data written to or read from the array at a location determined by the decoded row address signals and the decoded column address signals;
• a data path circuit operable to couple data signals corresponding to the data between the array and external data terminals of the memory device, the data path circuit including a plurality of write receivers each coupled to a respective one of the external data terminals and a plurality of read transmitters each coupled to a respective one of the external data terminals;
• a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;
• and
• a system for selecting redundant sets of memory cells, comprising
• a programmable circuit that is programmed to output an address corresponding to a defective set of memory cells;
• a defective memory cell decoder coupled to receive the address from the programmable circuit, the defective memory cell decoder outputting at least one shift control signal corresponding to the address from the programmable circuit, the at least one shift control signal indicating a shift direction for a select signal for the defective set corresponding to the address;
• and
• a select signal steering circuit coupled to receive the at least one shift control signal from the defective memory cell decoder, the select signal steering circuit being operable to shift in the direction indicated by the shift control signal the select signal for the defective set to an adjacent set of memory cells, to shift in the direction indicated by the at least one shift control signal the select signal for one of the sets to a redundant set of memory cells, and to shift in the direction indicated by the at least one shift control signal respective select signals for the sets intermediate the defective set and the one set to respective adjacent sets of memory cells.

A memory device, comprising:

• a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
• a column address circuit operable to receive and decode column address signals applied to the external address terminals;
• an array of memory cells operable to store data written to or read from the array at a location determined by the decoded row address signals and the decoded column address signals;
• a data path circuit operable to couple data signals corresponding to the data between the array and external data terminals of the memory device, the data path circuit including a plurality of write receivers each coupled to a respective one of the external data terminals and a plurality of read transmitters each coupled to a respective one of the external data terminals;
• a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;
• and
• a system for selecting redundant columns of memory cells, comprising
• a programmable circuit comprising a first circuit that may be programmed to output a first defective column address corresponding to a first defective column of memory cells, and a second circuit that may be programmed to output a second defective column address corresponding to a second defective column of memory cells;
• a defective column decoder coupled to receive the first and second defective column addresses from the programmable circuit, the defective column decoder being operable to output a first shift control signal corresponding to the first defective column address and to a first shift direction, and a second shift control signal corresponding to the second defective column address and a second shift direction that is opposite the first shift direction;
• and
• a column select steering circuit coupled to receive the first and second shift control signals from the defective column decoder, the column select steering circuit being operable responsive to the first shift control signal to shift in the direction indicated by the first shift control signal the select signal for the first defective column to an adjacent column of memory cells, to shift in the first direction the select signal for one of the columns to a first redundant column of memory cells, to shift in the first direction respective select signals for the columns intermediate the first defective column and the first redundant column to respective adjacent columns of memory cells, and wherein the select signal steering circuit is further operable responsive to the second shift control signal to shift in the second direction the select signal for the second defective column to an adjacent column of memory cells, to shift in the second direction the select signal for one of the columns to a second redundant set of memory cells, and to shift in the second direction respective select signals for the columns intermediate the second defective column and the second redundant column to respective adjacent sets of memory cells.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus to allow data to be output from the computer system;
• a data storage device coupled to the processor through the processor bus to allow data to be read from a mass storage device;
• a memory controller coupled to the processor through the processor bus;
• and
• a memory device coupled to the memory controller, the memory device comprising:
• a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
• a column address circuit operable to receive and decode column address signals applied to the external address terminals;
• an array of memory cells operable to store data written to or read from the array at a location determined by the decoded row address signals and the decoded column address signals;
• a data path circuit operable to couple data signals corresponding to the data between the array and external data terminals of the memory device, the data path circuit including a plurality of write receivers each coupled to a respective one of the external data terminals and a plurality of read transmitters each coupled to a respective one of the external data terminals;
• a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;
• and
• a system for selecting redundant sets of memory cells, comprising
• a programmable circuit that is programmed to output an address corresponding to a defective set of memory cells;
• a defective memory cell decoder coupled to receive the address from the programmable circuit, the defective memory cell decoder outputting at least one shift control signal corresponding to the address from the programmable circuit, the at least one shift control signal indicating a shift direction for a select signal for the defective set corresponding to the address;
• and
• a select signal steering circuit coupled to receive the at least one shift control signal from the defective memory cell decoder, the select signal steering circuit being operable to shift in the direction indicated by the shift control signal the select signal for the defective set to an adjacent set of memory cells, to shift in the direction indicated by the at least one shift control signal the select signal for one of the sets to a redundant set of memory cells, and to shift in the direction indicated by the at least one shift control signal respective select signals for the sets intermediate the defective set and the one set to respective adjacent sets of memory cells.

In a memory device in which each of a plurality of sets of memory cells are selected by a respective set select signal, a method of repairing a defective one of the sets of memory cells using a redundant set of memory cells, the method comprising:

• shifting the set select signal for the defective set of memory cells to a first of the plurality of sets of memory cells;
• shifting the set select signal for a second of the plurality of sets of memory cells to the redundant set of memory cells;
• and
• shifting the set select signals for a plurality of sets of memory cells, including the set select signal for the first set of memory cells, to respective other sets of memory cells.

A method of repairing at least two defective columns of memory cells using first and second redundant columns of memory cells, the method comprising:

• coupling a column select signal for a first defective column of memory cells to a first non-defective column of memory cells;
• coupling a column select signal for a second defective column of memory cells to a second non-defective column of memory cells;
• coupling a column select signal for a third non-defective column of memory cells to the first redundant column of memory cells;
• coupling a column select signal for a fourth non-defective column of memory cells to the second redundant column of memory cells;
• coupling a plurality of column select signals for columns intermediate the first non-defective column and the third non-defective column to respective adjacent columns of memory cells;
• and
• coupling a plurality of column select signals for columns intermediate the second non-defective column and the fourth non-defective column to respective adjacent columns of memory cells.

A method of coupling data to or from an array of memory cells arranged in rows and columns, the data being written to or read from a memory cell in a row and column corresponding to a row address and a column address, respectively, at least one of the rows or columns of memory cells being defective but being repairable by using a redundant row or column of memory cells, respectively, the method comprising:

• coupling data directed to or from a memory cell in the defective row or column that corresponds to a defective row or column address, respectively, to or from a memory cell in a first non-defective row or column, respectively, that corresponds to a first row or column address, respectively;
• coupling data directed to or from a memory cell in a second non-defective row or column corresponding to a second non-defective row or column address, respectively, to or from a memory cell in the redundant row or column, respectively;
• and
• coupling data directed to or from a plurality of memory cells in respective rows or columns corresponding to respective target row or column address that are intermediate the first non-defective row or column address, respectively, and the second non-defective row or column address, respectively, to rows or columns, respectively, that correspond to row or column addresses that are adjacent the respective target row or column addresses.