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US 6,807,110 B1Granted
Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorOsamu Wada
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a first bit line and a second bit line to which data read from first and second memory cells are supplied, respectively, when a word line is activated. A first dummy bit line is provided between the first and second bit lines without interposing any other bit line therebetween and fixed to the ground potential. A first and second sense amplifier amplify potentials on the first and second bit lines, respectively. A connection control section controls so that write data is supplied to the first bit line or second bit line after the word line is activated and before the first and second sense amplifiers operate.
Claims25
A semiconductor memory device comprising:
- first and second bit lines to which data read from first and second memory cells are supplied, respectively, when a word line is activated;
- a first dummy bit line provided between the first and second bit lines without interposing any other bit line therebetween and fixed to the ground potential;
- first and second sense amplifiers which amplify potentials on the first and second bit lines, respectively;
- and
- a connection control section which controls so that write data is supplied to the first bit line or the second bit line after the word line is activated and before the first and second sense amplifiers operate.
2 more elements
A semiconductor memory device comprising:
- a word line constituting gates of first and second memory cell transistors serving as parts of first and second memory cells and extending in a first direction;
- a wiring layer extending in the first direction above the word line and electrically isolated from the word line;
- first and second bit lines to which data read from first and second memory cells are supplied, respectively, when the word line is activated;
- first and second sense amplifiers which amplify potentials on the first and second bit lines, respectively;
- a connection control section which controls so that write data is supplied to the first bit line or the second bit line after the word line is activated and before the first and second sense amplifier operate;
- and
- a connection layer provided only between the first and second bit lines to electrically connect the word line with the wiring layer.
4 more elements
A semiconductor memory device comprising:
- first to n-th (n is a natural number of 2 or more) bit line groups which are sequentially arranged so as to be adjacent to each other and respectively comprise a plurality of bit lines adjacent to each other along a first direction, data read from a plurality of memory cells respectively connected with the plurality of bit lines being read to the bit lines;
- a plurality of first dummy bit lines provided between the bit lines forming a boundary between an i-th (i is a natural number of 1 to n−1) bit line group and an (i+1)-th bit line group without interposing any other bit line and fixed to the ground potential;
- a plurality of sense amplifiers provided for each of said plurality of the bit lines, respectively, and amplifying potentials on said plurality of bit lines;
- and
- a connection control section which controls so that write data is supplied to one of the first to n-th bit line groups after the word line is activated and before the sense amplifiers operate.
2 more elements
A semiconductor memory device comprising:
- a word line constituting gates of memory cell transistors serving as parts of memory cells and extending in a first direction;
- a wiring layer extending in the first direction above the word line and electrically isolated from the word line;
- first to n-th (n is a natural number of 2 or more) bit line groups which are sequentially arranged so as to be adjacent to each other and respectively comprise a plurality of bit lines adjacent to each other along a second direction different from the first direction, data read from a plurality of memory cells respectively connected with the plurality of bit lines being read to the bit lines;
- a plurality of sense amplifiers provided for each of said plurality of the bit lines, respectively, and amplifying potentials on said plurality of bit lines;
- a connection control section which controls so that write data is supplied to one of the first to n-th bit line groups after the word line is activated and before the sense amplifiers operate;
- and
- a connection layer provided only between the bit lines which form a boundary between an i-th (i is a natural number of 1 to n−1) bit line group and an (i+1)-th bit line group to electrically connect the word line with the wiring layer.
4 more elements
Dependencies are inferred from the claim text.