Semiconductor memory with shadow memory cell
AssigneeAdvanced Micro Devices, Inc.
InventorsWilliam A. McGee, Ognjen Milic-Strkalj, Bruce Alan Gieseke
Life of this patent
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Abstract
A memory system having a memory cell subject to read and write operations with shadow circuitry including a shadow cell configured to parallel operation of the memory cell. A wordline is connected to the memory cell and bitlines are connected to the memory cell and the shadow cell. Sense circuitry is connected to the bitlines for receiving data from the memory cell. An interlock cell is connected to the sense circuitry and the shadow cell to determine an occurrence of a non-redundant write operation, to provide the non-redundant write operation to the shadow cell, and to have the shadow cell prepare the bitlines for a read operation upon completion of the non-redundant write operation.
Claims20
A memory system comprising:
- a memory cell subject to read and write operations;
- shadow circuitry including a shadow cell configured to parallel operation of the memory cell;
- a wordline connected to the memory cell;
- bitlines connected to the memory cell and the shadow cell;
- sense circuitry connected to the bitlines for receiving data from the memory cell;
- and
- an interlock cell connected to the sense circuitry and the shadow cell to determine an occurrence of a write operation, to provide the write operation to the shadow cell, and to have the shadow cell prepare the bitlines for a read operation upon completion of the write operation.
A memory system comprising:
- a memory array including a memory cell subject to read and write operations;
- shadow circuitry including a shadow cell configured to parallel operation of the memory cell;
- a wordline connected to the memory cell responsive to a wordline signal to activate the memory cell for the read and write operations;
- bitlines connected to the memory cell and the shadow cell;
- sense circuitry connected to the bitlines to receive data from the memory cell and to amplify the data to provide an amplified data signal;
- and
- an interlock cell connected to the sense circuitry and the shadow cell responsive to clock, write-enable, amplified data, write, and data-in signals to determine an occurrence of a non-redundant write operation, to provide the write operation to the shadow cell, and to have the shadow cell prepare the bitlines for a read operation upon completion of the write operation.
Dependencies are inferred from the claim text.