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US 6,807,105 B2Granted
Fast program to program verify method
AssigneeHalo LSI, Inc.
InventorsSeiki Ogura, Tomoko Ogura, Nori Ogura
Life of this patent
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Abstract
In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
Claims4
A programming means for a dual storage site MONOS memory cell, comprising:
- a) a means for biasing a word gate to limit memory cell current,
- b) a means for biasing a first control gate to override threshold voltage of an unselected storage site beneath said first control gate,
- c) a means for coupling a source diffusion to a load device controlling cell current,
- d) a means for biasing a second control gate to inject electrons into a selected storage site beneath said second control gate,
- e) a means for suppressing a disturb condition in an unselected diffusion of an adjacent cell.
2 more elements
Dependencies are inferred from the claim text.