Nonvolatile semiconductor memory device and data program method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsFumitaka Arai, Akira Shimizu
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Abstract
A nonvolatile semiconductor memory device includes cell transistors connected to a plurality of wirings, word lines each commonly connected to the gate electrodes of those of the cell transistors which are arranged on a corresponding row, and driving circuits respectively connected to the plurality of wirings. The driving circuit includes a detection circuit which detects threshold voltage of the cell transistor in a verify operation, a storage circuit which stores threshold voltage detected and a potential setting circuit which sets potential of the wiring to at least three potentials based on the threshold voltage stored in the storage circuit in a program operation following the verify operation.
Claims32
A nonvolatile semiconductor memory device comprising:
- a plurality of wirings formed to extend in a first direction;
- memory cells containing nonvolatile memory cell transistors and connected to the plurality of wirings;
- word lines commonly connected to gate electrodes of the nonvolatile memory cell transistors arranged along a second direction which intersects the first direction;
- and
- driving circuits respectively connected to the plurality of wirings, each of the driving circuits including a detection circuit which detects threshold voltage of the nonvolatile memory cell transistor in a verify operation, a storage circuit which stores threshold voltage detected by the detection circuit and a potential setting circuit which sets potential of the wiring to at least three potentials based on the threshold voltage stored in the storage circuit in a program operation following the verify operation.
A data programming method of a nonvolatile semiconductor memory device comprising:
- programming data into a nonvolatile memory cell transistor,
- verifying threshold voltage of the nonvolatile memory cell transistor into which data has been programmed,
- setting potential of a bit line to program inhibition potential used to inhibit data programming if it is detected based on the result of verification that a sufficient amount of data has been programmed, and
- setting the potential of the bit line to one of program potential used to program data according to the threshold voltage of the nonvolatile memory cell transistor and at least one program suppression potential which lies between the program inhibition potential and the program potential and is used to program data while suppressing a program amount and additionally programming data into the nonvolatile memory cell transistor if it is detected based on the result of verification that a sufficient amount of data has not been programmed.
Dependencies are inferred from the claim text.