Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of memory cells arranged in rows and columns;
• a plurality of bit lines, provided corresponding to the memory cell columns, each connecting to the memory cells on a corresponding column connected;
• a plurality of sense amplifiers, electrically coupled commonly to a bit line connecting to an addressed memory cell of said plurality of memory cells, each for amplifying data of said addressed memory cell appearing on said bit line when activated;
• and
• sense control circuitry for controlling operations of said plurality of sense amplifiers in different ways from each other.

A semiconductor memory device comprising:

• a plurality of memory cells;
• reference circuitry for generating and outputting reference data having a condition thereof changeable;
• internal read circuitry for comparing data read from a selected memory cell of said plurality of memory cells with said reference data and reading the data in said selected memory cell on the basis of a result of comparison;
• and
• reference data control circuitry for selectively changing, in a specific operation mode, the condition for the reference data outputted by said reference circuitry in accordance with an address of said selected memory cell.