Nonvolatile semiconductor memory
AssigneeKabushiki Kaisha Toshiba
InventorHaruki Toda
Life of this patent
Estimating the term…
Abstract
One sub-data circuit is disposed for one selected bit line in a 4-level memory. The sub-data circuit has first and second latch circuits for serial accessing. In reading, an upper bit is latched through a sense latch in the first latch circuit. A reading operation of a lower bit is controlled to a value of the upper bit latched in the first latch circuit. In programming, an upper bit is latched in the first latch circuit. A program operation of a lower bit is controlled to a value of the upper bit latched in the first latch circuit.
Claims50
A nonvolatile semiconductor memory comprising:
- a memory cell to store n (n is a natural number of 2 or higher) bits;
- a first latch section to temporarily store 1 bit among the n bits in a first reading operation;
- and
- a second latch section to temporarily store the other 1 bit among the n bits in a second reading operation when the 1 bit has a first value, and in a third reading operation when the 1 bit has a second value.
A nonvolatile semiconductor memory comprising:
- a memory cell to store 2 bits;
- a first latch section to temporarily store 1 bit of the 2 bits in a first reading operation;
- and
- a second latch section to temporarily store the other 1 bit of the 2 bits in a second reading operation when the 1 bit has a first value, and in a third reading operation when the 1 bit has a second value.
A nonvolatile semiconductor memory comprising:
- a memory cell to store n (n is a natural number of 2 or higher) bits;
- a first latch section to temporarily store 1 bit among the n bits in a first writing operation;
- a second latch section to temporarily store the other 1 bit among the n bits in second and third writing operations;
- and
- a third latch section to store the other 1 bit in the second writing operation when the 1 bit has a first value, and in the third writing operation when the 1 bit has a second value.
A nonvolatile semiconductor memory comprising:
- a memory cell to store 2 bits;
- a first latch section to temporarily store 1 bit of the 2 bits in a first writing operation;
- a second latch section to temporarily store the other 1 bit of the 2 bits in second and third writing operations;
- and
- a third latch section to store the other 1 bit in the second writing operation when the 1 bit has a first value, and in the third writing operation when the 1 bit has a second value.
A nonvolatile semiconductor memory comprising:
- memory cells to store n (n is a natural number of 2 or higher) bits;
- sub-data circuits disposed corresponding to the memory cells to carry out a reading/writing operation for the memory cells;
- and
- a first shift register to sequentially select the sub-data circuits one by one,
- wherein each of the sub-data circuits has a first latch section to temporarily store 1 bit among the n bits, and the 1 bit is serially outputted from the first latch section of the sub-data circuit selected by the shift register.
A read method for a memory cell which stores 2 bits by 0, first, second and third threshold levels (0 threshold level<first threshold level<second threshold level<third threshold level), comprising:
- carrying out a first reading operation for the memory cell by applying a first reading potential between the first threshold level and the second threshold level to a selected word line;
- determining that 1 bit of the 2 bits has a first value when a threshold value of the memory cell is the 0 or first threshold level;
- determining that the 1 bit has a second value when a threshold value of the memory cell is the second or third threshold level;
- then
- (1) if the 1 bit has the first value, carrying out a second reading operation for the memory cell by applying a second reading potential between the 0 threshold level and the first threshold level to the selected word line, determining that the other 1 bit of the 2 bits has a first value when a threshold value of the memory cell is the 0 threshold level, and determining that the other 1 bit has a second value when a threshold value of the memory cell is the first threshold level;
- and
- (2) if the 1 bit has the second value, carrying out a third reading operation for the memory cell by applying a third reading potential between the second threshold level and the third threshold level to the selected word line, determining that the other 1 bit has a first value when a threshold value of the memory cell is the second threshold level, and determining that the other 1 bit has a second value when a threshold value of the memory cell is the third threshold level
- (an order of (1) and (2) may be reversed).
A program method for a memory cell which stores 2 bits by 0, first, second and third threshold levels (0 threshold level<first threshold level<second threshold level<third threshold level), comprising:
- setting a threshold value of the memory cell to the 0 threshold level;
- then carrying out a first writing operation for the memory cell, maintaining the threshold value of the memory cell at the 0 threshold level when program data for 1 bit of the 2 bits is a first value, and changing the threshold value of the memory cell to the second threshold level when program data for the 1 bit is a second value;
- then
- (1) carrying out a second writing operation for the memory cell, if the program data for the 1 bit is the first value, when program data for the other 1 bit of the 2 bits is the first value, maintaining the threshold value of the memory cell at the 0 threshold level, and changing the threshold value of the memory cell to the first threshold level when the program data for the other 1 bit is the second value;
- and
- (2) carrying out a third writing operation for the memory cell, if the program data for the 1 bit is the second value, when the program data for the other 1 bit is the first value, maintaining the threshold value of the memory cell at the second threshold level, and changing the threshold value of the memory cell to the third threshold level when the program data for the other 1 bit is the second value
- (an order of (1) and (2) may be reversed).
Dependencies are inferred from the claim text.