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US 6,807,081 B2Granted
Semiconductor memory circuit hard to cause soft error
AssigneeRenesas Technology Corp.
InventorKoji Nii
Life of this patent
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Abstract
A memory cell of SRAM includes: two N-channel MOS transistors connected in series between a first storage node and a line of a ground potential and two N-channel MOS transistors connected in series between a second storage node and a line of a ground potential. Since no storage data is inverted unless one α-particle passes through two N-channel MOS transistors, a soft error hard to occur.
Claims19
A semiconductor memory circuit formed on a SOI comprising:
- two inverters connected between first and second storage nodes, an input node of each inverter being connected to an output node of the other inverter, wherein
- said inverters each includes:
- plural first MOS transistors with a first conductivity type, connected in series between a line of a first power supply potential and the output node, and whose gate electrodes are all connected to the input node;
- and
- a MOS second transistor with a second conductivity type, connected between a line of a second power supply potential and the output node, and whose gate electrode is connected to the input node, wherein
- each said first MOS transistor has a body region provided beneath the sate electrode, and the body region of each said first MOS transistor is spaced apart from the body region of another said first MOS transistor.
3 more elements
Dependencies are inferred from the claim text.