Semiconductor input/output circuit arrangement
AssigneeSTMicroelectronics S.r.l.
InventorsWilliam Thies, Nicolas Froidevaux
Life of this patent
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Abstract
A method produces a semiconductor circuit with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.
Claims20
A method of producing a semiconductor circuit with an area saving in comparison with a conventional circuit using library cells, each of the circuits having active circuitry, an input/output interface comprising separate IO cells and pads for external connection to the active circuitry via the IO cells, comprising:
- determining a ratio of power/ground pads to input/output pads for the interface in the conventional circuit;
- determining a width of each IO cell of the conventional circuit;
- producing IO cells of a width substantially equal to the width of each IO cell of the conventional circuit multiplied by a factor based on the ratio of power/ground pads to input/output pads, but of corresponding reduced height;
- and
- producing power/ground pads and input/output pads for connection to the IO cells of the semiconductor circuit grouped together in the ratio determined for the conventional circuit.
A semiconductor circuit with an area saving in comparison with a usual arrangement having active circuitry, an input/output interface comprising separate IO cells and pads for external connection to the active circuitry via the IO cells, comprising:
- IO cells of greater than normal width and corresponding reduced height, wherein the width is multiplied, compared to a width of the IO cells of the usual arrangement, by a factor based on a ratio of power/ground pads to input/output pads determined for the usual arrangement;
- and
- power/ground pads and input/output pads for connection to the IO cells of the semiconductor circuit, grouped together in the ratio of power/ground pads to input/output pads.
A semiconductor circuit, comprising:
- active circuitry;
- an input/output interface having a plurality of IO cells, one of the IO cells having associated IO and supply or ground pads but not having an adjacent ESD cell;
- pads for external connection to the active circuitry via the input/output interface;
- and
- a separate ESD protection cell provided within the input/output interface for protection of the active circuitry and input/output circuitry.
A semiconductor circuit, comprising:
- active circuitry;
- input/output circuitry;
- and
- pads for external connection to the active circuitry via the input/output circuitry;
- wherein the input/output circuitry includes a plurality of IO library cells of fixed width, the IO library cells having connected IO pads and supply or source pads in a fixed ratio;
- and at least a subset of the IO library cells includes supply/source connections, but no ESD circuitry connected directly with the supply/source connections.
Dependencies are inferred from the claim text.