Integrated circuit for targeted bitlength manipulation for serial data transmission
AssigneePhoenix Contact GmbH & Co. KG
InventorMichael Hoffmann
Life of this patent
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Abstract
An integrated circuit for generating targeted bitlength manipulation of a transmitter for output of a serial datastream. A control unit (5) provides instructions regarding respective partial bits in a form of a partial bit vector (7) depending on bit statuses to be sent, and determines bitlengths for the serial datastream for output (9) to a wire or a signaling converter. The datastream (9) is generated using two partial bit register chains (14a-d, 15a-d), whose serial outputs (16, 17) are connected using a joining gate.
Claims36
An improved integrated circuit for generating targeted bitlength manipulation of a transmitter for output of a serial datastream, wherein a control unit (5) provides instructions regarding respective partial bits in a form of a partial bit vector (7) depending on bit statuses, so that bitlengths are determined for the serial datastream for output (9) to one of a wire and a signaling converter, said improvement comprising each bit to be outputted consisting of at least two partial bit register chains (14a-d, 15a-d) which are provided to generate the bits for outputting, wherein the improvement comprises:
- an individual system clock (16, 19) being provided for each partial bit register chain;
- and
- when two partial bit register chains are used, a first partial bit resister chain is locked with a non phase-shifted system clock (6) and a second partial bit register chain is clocked with a system clock (19) that is phase-shifted through 180 degrees.
An improved integrated circuit for generating targeted bitlength manipulation of a transmitter for output of a serial datastream, wherein a control unit (5) provides instructions regarding respective partial bits in a form of a partial bit vector (7) depending on bit statuses, so that bitlengths are determined for the serial datastream for output (9) to one of a wire and a signaling converter, said improvement comprising each bit to be outputted consisting of at least two partial bit register chains (14a-d, 15a-d) which are provided to generate the bits for outputting;
- wherein the improvement comprises when four partial bit register chains are used, a first partial bit register chain is clocked with a non phase-shifted system clock and a second partial bit register chain is clocked with a system clock that is phase-shifted through 90 degrees, and a third partial bit register chain is clocked with a system clock that is phase-shifted through 180 degrees, and a fourth partial bit register chain is clocked with a system clock that is phase-shifted through 270 degrees.
An improved integrated circuit for generating targeted bitlength manipulation of a transmitter for output of a serial datastream, wherein a control unit (5) provides instructions regarding respective partial bits in a form of a partial bit vector (7) depending on bit statuses, so that bitlengths are determined for the serial datastream for output (9) to one of a wire and a signaling converter, said improvement comprising:
- each bit to be outputted consisting of at least two partial bit register chains (14a-d, 15a-d) which are provided to generate the bits for outputting;
- and
- when n partial bit register chains are used, each successive bit register chain is clocked with a corresponding non-phase-shift system clock that is phase-shifted through 360°/n.
Dependencies are inferred from the claim text.