Low loss high Q inductor
AssigneeMicron Technology, Inc.
InventorsKie Y. Ahn, Leonard Forbes
Life of this patent
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Abstract
A high Q inductive clement with low losses, high inductance and high efficiency is disclosed. The high Q inductive element with one or more inductive loops is formed over a silicon micro structure with thin support elements formed by deep plasma etching in bulk silicon. The support elements, which may have different configurations, such as walls or columns, provide mechanical stability to the inductive loops and reduce the parasitic capacitance and the losses to the substrate.
Claims29
An inductive element comprising:
- a semiconductor substrate including a cavity and having at least one semiconductor wall formed within said cavity, said semiconductor wall including a top surface;
- an oxide insulating layer provided on said top surface;
- and
- a conductive element located over said oxide insulating layer, said conductive element being supported by said semiconductor wall and including at least one loop.
The semiconductor device having a substrate and a cavity structure, a portion of said substrate being contact with said cavity, said device comprising:
- a plurality of semiconductor support element provided in said cavity, said plurality of semiconductor support element extending radially from a center portion of said cavity structure and having a height of about 200 microns, said plurality of semiconductor support elements including a top surface;
- an insulating layer provided on said top surface;
- a barrier layer provided over said insulating layer;
- and
- at least one electrically conductive loop formed over said barrier layer, said electrically conductive loop being supported by said semiconductor support elements.
An inductive element comprising:
- a semiconductor substrate including a cavity and having a plurality of semiconductor walls formed in said cavity, said semiconductor walls including silicon and extending radially from a center portion of said semiconductor substrate;
- a silicon oxide layer provided on top surfaces of said semiconductor walls;
- and
- at least one spiral loop located over said silicon oxide layer, said at least one spiral loop being supported by said semiconductor walls and having a thickness of about 0.3 microns to about 0.5 microns.
An inductive element comprising:
- a semiconductor substrate including a cavity and having a plurality of semiconductor columns formed in said cavity, said semiconductor columns including silicon and extending radially from a center portion of said semiconductor substrate;
- a silicon oxide layer provided on top surfaces of said semiconductor columns;
- and
- at least one spiral loop located over said silicon oxide layer, said at least one spiral loop being supported by said semiconductor walls and having a thickness of about 0.3 microns to about 0.5 microns.
Dependencies are inferred from the claim text.