Operational amplifier

An operational amplifier for use with high and low potential power supplies and for receiving an input current, the operational amplifier comprising:

• a first output transistor connected to the high potential power supply and having a control terminal;
• a second output transistor connected between the first output transistor and the low potential power supply and having a control terminal, with an output voltage being available at an output node between the first output transistor and the second output transistor;
• and
• a drive unit connected to the first and second output transistors to drive the first and second output transistors in accordance with the input current, wherein the drive unit including:
• a current source connected to the high potential power supply;
• a first current mirror circuit connected to the current source;
• a second current mirror circuit connected between the first current mirror circuit and the low potential power supply;
• and
• a first resistor connected between the second current mirror circuit and the low potential power supply;
• wherein the control terminal of the second output transistor is connected to a first node between the first and second current mirror circuits, the control terminal of the first output transistor is connected to a second node between the current source and the first current mirror circuit, and the input current is supplied to a third node between the second current mirror circuit and the first resistor.

An operational amplifier for use with high and low potential power supplies and a current source, the operational amplifier comprising:

• a first PNP transistor having a collector connected to the current source, a base connected to the collector, and an emitter connected to the high potential power supply;
• a second PNP transistor having a base connected to the base of the first PNP transistor and an emitter connected to the high potential power supply;
• a third PNP transistor having an emitter connected to a collector of the second PNP transistor;
• a fourth PNP transistor having an emitter connected to the collector of the second PNP transistor and to the emitter of the third PNP transistor;
• a fifth PNP transistor having a base connected to the bases of the first and second PNP transistors and an emitter connected to the high potential power supply;
• a sixth PNP transistor having a base connected to the base of the fifth PNP transistor and an emitter connected to the high potential power supply;
• a first NPN transistor having a collector and a base connected to a collector of the fifth PNP transistor and an emitter connected to a collector of the fourth PNP transistor;
• a second NPN transistor having a base connected to the collector of the fifth PNP transistor, a collector connected to the collector of the sixth PNP transistor, and an emitter connected to a collector of the third PNP transistor;
• a third NPN transistor having a collector and a base connected to the emitter of the first NPN transistor and an emitter connected to the low potential power supply;
• a fourth NPN transistor having a collector connected to the emitter of the second NPN transistor, a base connected to the base of the third NPN transistor, and an emitter connected to the low potential power supply;
• a seventh PNP transistor having an emitter connected to the high potential power supply and a base connected to the collectors of the sixth PNP transistor and the second NPN transistor;
• and
• a fifth NPN transistor having a collector connected to a collector of the seventh PNP transistor, a base connected to the emitter of the second NPN transistor and to the collector of the fourth NPN transistor, and an emitter connected to the low potential power supply.