Delay circuit and synchronous delay apparatus

A synchronous delay apparatus, comprising:

• an input buffer to which an input clock signal is inputted;
• a delay monitor circuit connected to an output terminal of said input buffer;
• a first delay element group consisted of a plurality of delay elements connected to an output terminal of said delay monitor circuit;
• a second delay element group consisted of a plurality of delay elements connected to an output terminal of said first delay element group;
• an output buffer connected to an output terminal of said second delay element group;
• and
• a control circuit which controls delay time of said first and second delay element groups,
• wherein said delay monitor circuit has delay amount relating to the delay amounts of said first and second delay element groups;
• each of said delay elements composing said first and second delay element groups includes:
• a plurality of delay blocks connected in series, each having a first complementary input terminal to which a first complementary signal is inputted, a second complementary input terminal to which a second complementary signal is inputted, and a complementary output terminal which outputs a third complementary signal delaying by selecting one of said first and second complementary signals based on logic of a delay selection signal,
• said complementary output terminal of said delay blocks except for said delay block of last stage being connected to said second complementary input terminal of the subsequent delay block, respectively,
• a complementary delay signal delaying said first complementary signal in accordance with logic of said delay selection signal being outputted from said complementary output terminal of said delay block of last stage, and
• the same first complementary signal is inputted to said first complementary input terminals of said plurality of delay blocks, respectively, and
• one of said plurality of delay blocks connected in series being selected in accordance with logic of said delay selection signal, the selected delay block outputting said third complementary signal delaying said first complementary signal, and a delay block not selected outputting said third complementary signal delaying said second complementary signal.