Method and logic/memory module for correcting the duty cycle of at least one control/reference signal

A method for correcting a given duty cycle between a first time period of a first level state and a second time period of a second level state of at least a periodic control/reference signal of a logic/memory unit to form a desired corrected duty cycle, which comprises:

• setting the desired corrected duty cycle between the time periods of the first and second level states of the periodic control/reference signal by changing at least one of a rising time period of a rising edge and a fall time period of a falling edge by a predefinable correction time period;
• correcting a duty cycle of a further periodic control/reference signal having essentially identical level states as the first periodic control/reference signal by offsetting by half of a period the level states of the further periodic control/reference signal with respect to the level states of the periodic control/reference signal and dynamically switching four power sources with the uncorrected periodic control/reference signals by:
• loading a first capacitive output node of the logic/memory unit during the rising edge of the periodic control/reference signal with a base current, the base current being changed by a current correction factor;
• recharging the first capacitative output node during the falling edge of the first periodic control/reference signal with the base current, the base current being changed by the current correction factor;
• loading a second capacitive output node during a rising edge of the further periodic control/reference signal with the base current, the base current being changed by the current correction factor;
• and
• recharging the second capacitative output node during a falling edge of the further periodic control/reference signal with the base current, the base current being changed by the current correction factor;
• and tapping the corrected control/reference signals at the first and second capacitive output node with the desired duty cycle.

A method for correcting a given duty cycle between a first time period of a first level state and a second time period of a second level state of at least a periodic control/reference signal of a logic/memory unit to form a desired corrected duty cycle, which comprises:

• setting the desired corrected duty cycle between the time periods of the first and second level states of the periodic control/reference signal by changing at least one of a rising time period of a rising edge and a fall time period of a falling edge by a predefinable correction time period;
• correcting a duty cycle of a further periodic control/reference signal having essentially identical level states as the first periodic control/reference signal by offsetting by half of a period the level states of the further periodic control/reference signal with respect to the level states of the periodic control/reference signal;
• essentially statically charging two capacitive output nodes of the logic/memory module with a base current, the base current being changed by a current correction factor;
• dynamically switching a discharging of the two capacitive output nodes by the uncorrected periodic control/reference signals in order to discharge the capacitative output node that was previously statically charged with a base current reduced by the current correction factor by applying the base current increased by the current correction factor;
• and
• discharging again the capacitive output node previously statically charged with the base current increased by the current correction factor with the base current reduced by the current correction factor.