Method and system for clock deskewing using a continuously calibrated delay element in a phase-locked loop

A system for clock deskewing using a continuously calibrated delay element in a phase-locked loop, comprising:

• a delay element operable to receive a feedback signal and a skew select signal and to delay the feedback signal based on the skew select signal to generate a delay output signal;
• a phase detector coupled to the delay element, the phase detector operable to receive an external clock signal and the delay output signal and to generate a phase detector signal based on the external clock signal and the delay output signal;
• a voltage-controlled oscillator coupled to the phase detector, the voltage-controlled oscillator operable to receive the phase detector signal and to generate an output clock signal based on the phase detector signal;
• and
• a distribution network coupled to the voltage-controlled oscillator, the distribution network operable to receive the output clock signal and to generate a skewed clock signal and the feedback signal based on the output clock signal;
• the delay element comprising:
• a delay element calibration engine operable to continuously calibrate the delay element;
• and
• a digital-to-analog converter coupled to the delay element calibration engine, the digital-to-analog converter operable to receive a digital-to-analog converter signal from the delay element calibration engine and to adjust an amount of current generated based on the digital-to-analog converter signal.

A method for clock deskewing using a continuously calibrated delay element in a phase-locked loop, comprising:

• receiving an external clock signal;
• receiving a skew select signal;
• delaying the external clock signal based on the skew select signal to generate a delay output signal;
• providing the delay output signal to a phase detector;
• receiving a feedback signal and the delay output signal at the phase detector;
• generating a phase detector signal based on the feedback signal and the delay output signal;
• and
• generating a skewed clock signal and the feedback signal based on the phase detector signal.

A phase-locked loop, comprising:

• a delay element operable to receive a feedback signal and a skew select signal and to delay the feedback signal based on the skew select signal to generate a delay output signal;
• a phase detector coupled to the delay element, the phase detector operable to receive an external clock signal and the delay output signal and to generate a phase detector signal based on the external clock signal and the delay output signal;
• and
• a voltage-controlled oscillator coupled to the phase detector, the voltage-controlled oscillator operable to receive the phase detector signal and to generate an output clock signal based on the phase detector signal;
• the delay element comprising a delay element calibration engine operable to continuously calibrate the delay element and a digital-to-analog converter coupled to the delay element calibration engine, the digital-to-analog converter operable to receive a digital-to-analog converter signal from the delay element calibration engine and to adjust an amount of current generated based on the digital-to-analog converter signal.