Reduced complexity linear phase detector

A clock recovery circuit comprising:

• a phase detector circuit;
• the phase detector circuit comprising:
• first, second and third latches connected in series, each of the latches having a data input, a data output and a clock input, the data output of the first latch being coupled to the data input of the second latch, the data output of the second latch being coupled to the data input of the third latch;
• reference signal generation circuitry having at least a first input coupled to the data output of the second latch and a second input coupled to the data output of the third latch, the reference signal generation circuitry being configured to generate an output corresponding to a reference signal;
• and
• error signal generation circuitry having at least a first input coupled to the data input of the first latch and a second input coupled to the data output of the second latch, the error signal generation circuitry being configured to generate an output that is indicative, relative to the reference signal, of phase error of a clock signal;
• and
• signal processing circuitry coupled to the phase detector circuit and configured to process the outputs of the reference signal generation circuitry and error signal generation circuitry to generate a signal having a characteristic which varies as a function of the phase error of the clock signal.

An integrated circuit comprising a plurality of phase detector circuits, at least a given one of the phase detector circuits comprising:

• first, second and third latches connected in series, each of the latches having a data input, a data output and a clock input, the data output of the first latch being coupled to the data input of the second latch, the data output of the second latch being coupled to the data input of the third latch;
• reference signal generation circuitry having at least a first input coupled to the data output of the second latch and a second input coupled to the data output of the third latch, the reference signal generation circuitry being configured to generate an output corresponding to a reference signal;
• and
• error signal generation circuitry having at least a first input coupled to the data input of the first latch and a second input coupled to the data output of the second latch, the error signal generation circuitry being configured to generate an output that is indicative, relative to the reference signal, of phase error of a clock signal.