Circuit for a lossless capacitive pump
AssigneeSiemens Milltronics Process Instruments, Inc.
InventorClaude Mercier
Life of this patent
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Abstract
A capacitive pump circuit suitable for use in loop powered level measurement and time of flight ranging systems. The capacitive pump circuit comprises an input buffer, a level shifter and an output stage. The input buffer receives a clocking signal which is also coupled to the input of the output stage through the level shifter. The output from the input buffer is switched by the output stage to charge a capacitor and generate a voltage output which has the opposite polarity of the voltage supply rail. According to another aspect, a capacitive voltage doubler circuit is provided which is also suitable for use in loop powered level measurement and time of flight ranging systems.
Claims15
A capacitive pump circuit comprising:
- (a) a buffer having a supply input coupled to a voltage supply rail, an input for receiving a clocking signal and having an output;
- (b) a level shifter having an input for receiving said clocking signal and an output;
- (c) an output stage having a first input, a second input, and an output port for outputting a voltage, and an output capacitor, said first input being coupled to the output of said buffer through another capacitor, said second input being coupled to the output of said level shifter;
- (d) said output stage including first and second transistors connected in a push-pull configuration, said first and second transistors having a control terminal connected to the output of said level shifter, said first transistor having an input terminal connected to a ground rail and an output terminal connected to an input terminal of said second transistor, said connection forming the first input for said output stage, and said second transistor having an output terminal, said output terminal forming said output port, and said output capacitor having one terminal coupled to said output terminal and another terminal coupled to said ground rail.
The capacitive pump circuit as claimed 2, wherein said first and second transistors comprise MOSFET devices, each having a source, drain and gate terminals, the gate terminals of said first and second transistors being connected to the output of said level shifter, the source terminal of said first transistor being connected to the ground rail and the drain terminal of said first transistor being connected to the source terminal of said second transistor, and the drain terminal of said second transistor forming said output port.
A capacitive voltage doubler circuit comprising:
- (a) a buffer having a supply input coupled to a voltage supply rail, an input for receiving a clocking signal and having an output;
- (b) a level shifter having an input for receiving said clocking signal and an output;
- (c) an output stage having a first input, a second input, and an output port for outputting a voltage, and an output capacitor, said first input being coupled to the output of said buffer through another capacitor, said second input being coupled to the output of said level shifter;
- (d) said output stage including first and second transistors connected in a push-putt configuration, said first and second transistors each having a control terminal, an input terminal, and an output terminal, the control terminals for said first and said second transistors being connected to the output of said level shifter, the output terminal of said first transistor being connected to one terminal of said output capacitor to form said output port, and the input terminal of said first transistor being connected to the output terminal of said second transistor end one terminal of the capacitor coupled to the output of said buffer, said connection forming the first input for said output stage, and the input terminal of said second transistor being coupled to the other terminal of said output capacitor and the supply voltage rail.
The capacitive voltage doubler circuit as claimed 9, wherein said first and second transistors comprise MOSFET devices, each having a source, drain and gate terminals, the gate terminals of said first and second transistors forming said second input and being connected to the output of said level shifter, the drain terminal of said first transistor being connected to one terminal of sold output capacitor and forming said output port, the source terminal of said first transistor being connected to the drain terminal of said second transistor and forming said first input, and the source terminal of said second transistor being connected to said voltage supply rail and the other terminal of said output capacitor.
Dependencies are inferred from the claim text.