Multiple data rate interface architecture
AssigneeAltera Corporation
InventorsPhilip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
Life of this patent
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Abstract
Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
Claims16
A programmable logic device (PLD) comprising:
- input/output (I/O) interface having a first plurality of I/O register blocks, the first plurality of I/O register blocks being partitioned into a second plurality of I/O sections each I/O section having N data I/O register blocks and a strobe circuit, wherein each of the N data I/O register blocks is configured to store multiple bits of data, and each strobe circuit is configured to generate a local strobe signal that drives a local clock line coupling to clock inputs of the N data I/O register blocks, the N data I/O register blocks and the strobe circuit in each I/O section being coupled to a corresponding number of device pins;
- and
- programmable logic circuitry coupled to the I/O interface.
The PLD of claim wherein a separate master phase control circuit is provided for I/O sections in each of the third plurality of I/O banks.
A method of operating a programmable logic device (PLD) comprising:
- receiving N groups of data bits each group having M data signals and a corresponding data strobe signal;
- partitioning I/O register blocks inside the PLD into a corresponding N I/O modules, each module having M I/O register blocks and a strobe circuit coupled to receive a respective group of M data signals and data strobe signal;
- and
- driving clock inputs of the M I/O register blocks in each of the N I/O modules using an independent clock network that is local to each of the N I/O modules.
Dependencies are inferred from the claim text.