Semiconductor integrated circuit device and fault-detecting method of a semiconductor integrated circuit device
AssigneeRenesas Technology Corp.
InventorIchiro Kohno
Life of this patent
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Abstract
A semiconductor integrated circuit device which shortens the time required for testing a divided logic circuit to reduce test cost and a fault-detecting method therefor. The logic circuit is divided into N logic blocks using N+1 scan paths comprises of scan flip-flops each having selectors for selectively picking up the output signals of storage elements which are fed back to the storage elements. A common scan operation may then be carried out on these logic blocks (Logic 1-to Logic N), and a testing operation may be continuously carried out on the logic blocks. The present invention preferably eliminates the overlaps in conventional scan operations, resulting in a shorter test time.
Claims5
A semiconductor integrated circuit device, including storage elements and logic gates which constitute a scan flip-flop, said device comprising:
- a first storage element having inputs and an output;
- a first logic gate having inputs and an output, wherein the inputs to said first logic gate include a first signal, the output signal of the first storage element, and a second signal;
- a second logic gate having inputs and an output, wherein the inputs to said second logic gate include the output signal of the first logic gate, a third signal, and a fourth signal, wherein the output signal of the second logic gate and a fifth signal are input into the first storage element;
- a second storage element having inputs and an output;
- and
- a third logic sate having inputs and an output, wherein the inputs to said third logic gate include the output signal of the first storage element, the output signal of the second storage element, and the fourth signal, further wherein the inputs of said second storage element include the output signal of the third logic gate and the fifth signal.
Dependencies are inferred from the claim text.