Circuit and method for interfacing to a bus channel

A method for interfacing to a bus, the method comprising the steps of:

• providing an external termination pad configured to be coupled to a bus line;
• tracking a difference between a terminating voltage for the bus and a first reference voltage for the bus to produce a second reference voltage;
• generating a reference current that corresponds to the second reference voltage;
• sourcing the reference current to an amplifier;
• amplifying a data signal with the amplifier to drive the external termination pad;
• generating a current control signal by comparing a voltage at the external termination pad to the second reference voltage;
• and
• sourcing an on-die termination current to the external termination pad that corresponds to the current control signal.

A device for interfacing to a bus through an external termination pad, the device comprising:

• means for tracking a difference between a terminating voltage for the bus and a first reference voltage for the bus to produce a second reference voltage;
• means for generating a reference current that corresponds to the second reference voltage;
• means for sourcing the reference current to an amplifier;
• means for amplifying a data signal with the amplifier to drive the external termination pad;
• means for generating a current control signal by comparing a voltage at the external termination pad to the second reference voltage;
• and
• means for sourcing an on-die termination current to the external termination pad that corresponds to the current control signal.

A bus system, the bus system including:

• at least one bus line;
• a termination voltage terminal coupled to the bus line and configured to have an external termination voltage;
• a termination resistor coupled between the termination voltage terminal and the bus line and having an external resistance value;
• and
• a bus interface device having an external termination pad coupled to the bus line, the bus interface device being configured to receive the termination voltage and an external reference voltage and compare the termination voltage and an external reference voltage in order to generate an output low reference voltage, the device being further configured to compare the output low reference voltage to a voltage at the external termination pad in order to generate a current control signal, where the device includes a current source configured to source current to the external termination pad responsive to the current control signal.

A current control circuit for a bus interface, the circuit comprising:

• a first transistor having first and second current terminals and a control terminal, the first current terminal of the first transistor being coupled to a first power supply terminal and the control terminal of the first transistor being coupled to a circuit node configured to receive a first sampled logic voltage;
• a first current source being coupled between the second current terminal of the first transistor and a second power supply terminal;
• a second transistor having first and second current terminals and a control terminal, the first current terminal of the second transistor being coupled to the first power supply terminal and the control terminal of the second transistor being coupled to a circuit node configured to receive a second sampled logic voltage;
• a second current source being coupled between the second current terminal of the second transistor and the second power supply terminal;
• a third transistor having first and second current terminals and a control terminal, the second current terminal of the third transistor being coupled to the second power supply terminal;
• a first resistor coupled between the control terminal of the third transistor and the second current terminal of the first transistor;
• a second resistor coupled between the control terminal of the third transistor and the second current terminal of the second transistor;
• a third current source being coupled between the first current terminal of the third transistor and the first power supply terminal;
• a fourth transistor having first and second current terminals and a control terminal, the first current terminal of the fourth transistor being coupled to the first power supply terminal and the control terminal of the fourth transistor being coupled to a first external termination pad configured to receive a reference voltage;
• a fourth current source being coupled between the second current terminal of the fourth transistor and the second power supply terminal;
• a fifth transistor having first and second current terminals and a control terminal, the second current terminal of the fifth transistor being coupled to the second power supply terminal and the control terminal of the fourth transistor being coupled to the second current terminal of the fourth transistor;
• a fifth current source being coupled between the first current terminal of the fifth transistor and the first power supply terminal;
• and
• a comparator having inverting and non-inverting input terminals and an output terminal, the non-inverting input terminal being coupled to the first current terminal of the third transistor and the inverting terminal being coupled to the first current terminal of the fifth transistor, where the comparator is configured to compare the voltages received at the inverting and non-inverting input terminals and output a current control signal.

A circuit for sensing an external resistance coupled to an external termination pad and adjusting a current drawn from the external termination pad, the circuit comprising:

• an amplifier having inverting and non-inverting input terminals and an output terminal, the non-inverting input terminal being coupled to a circuit node configured to receive a reference voltage;
• a first transistor having first and second current terminals and a control terminal, the control terminal of the first transistor being coupled to the output terminal of the first amplifier and the first current terminal of the first transistor being coupled to the inverting input terminal of the first amplifier;
• a first resistive load coupled between the first current terminal of the first transistor and a circuit node configured to receive a termination voltage;
• a second transistor having first and second current terminals and a control terminal, the control terminal of the second transistor being coupled to the first current terminal of the second transistor and the second current terminal of the first transistor and the second current terminal of the second transistor is coupled to a power supply terminal;
• a third transistor having first and second current terminals and a control terminal, where the third transistor is larger than the second transistor by a selected ratio, and where the control terminal of the third transistor is coupled to the control terminal of the second transistor and the second current terminal of the third transistor is coupled to the power supply terminal;
• a second resistive load coupled between the first current terminal of the third transistor and the circuit node configured to receive the termination voltage;
• a comparator having inverting and non-inverting input terminals and an output terminal, the inverting input terminal being coupled to the first current terminal of the third transistor and the non-inverting input terminal being coupled to the external termination pad;
• a circuit node configured to receive a reference voltage;
• a current logic control circuit having an input terminal coupled to the output terminal of the comparator and an output terminal for outputting the current control signal, where the current logic control circuit is configured to transform an output signal from the comparator into a current control signal;
• and
• a current source coupled between the external termination pad and the power supply terminal, the current source being configured to receive the current control signal and conduct a current that is proportional to the current control signal.

A method for controlling current in a bus interface circuit, the method comprising the steps of:

• charge coupling the circuit to a first node for receiving a first sampled logic voltage;
• modulating a current from a first power supply terminal to a first circuit node responsive to the first sampled logic voltage;
• charge coupling the circuit to a second node for receiving a second sampled logic voltage;
• modulating a current from the first circuit node to a second power supply terminal responsive to the second sampled logic voltage;
• stepping up a voltage at the first circuit node to create a midrange voltage;
• charge coupling the circuit to a third node for receiving a reference voltage;
• modulating a current from the first power supply terminal to the second power supply terminal through a second circuit node responsive to the reference voltage;
• stepping up a voltage at the second circuit node to create a stepped up reference voltage;
• and
• comparing the midrange voltage and the stepped up reference voltage in order to generate a current control signal.

A method for sensing an external resistance coupled to an external termination pad and adjusting a current drawn from the external termination pad, the method comprising the steps of:

• comparing a reference voltage to a termination voltage through a first resistive load;
• modulating a current between the termination voltage and a ground voltage through the first resistive load based upon the comparison to produce a first reference current;
• mirroring the first reference current through a pair of transistors having a predetermined size ratio in order to produce a second reference current;
• sinking the second reference current from the termination voltage through a second resistive load to produce an output low reference voltage;
• comparing the output low reference voltage to a voltage at the external termination pad to produce a current control signal;
• and
• sinking current from the external termination pad to the ground voltage responsive to the current control signal.