Method and system for improving quiescent currents at low output current levels
AssigneeNational Semiconductor Corporation
InventorErnest Armand Bron
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AssigneeNational Semiconductor Corporation
InventorErnest Armand Bron
Estimating the term…
An oscillator circuit is coupled to an enable pin of an Voltage regulator so that total power consumption is minimized in the application. A filter capacitor is coupled to the Voltage regulator such that current is supplied to the load (the application) while the Voltage regulator is disabled. The frequency of the oscillator circuit is low such that power consumption by the oscillator is minimal. The duty cycle (DC) of the oscillator circuit is selected so that the output voltage across the load does not drop below minimum voltage requirements in the application. The total current (I) that is consumed by the system corresponds to: I=DC*Idq+(1−DC)*Iq+Iosc+Iapp, where Iq corresponds to the shutdown current of the LDO, Idq is the ground current of the LDO, Iosc is the oscillator operating current, and Iapp is the average current consumed by the application.
An apparatus for reducing power requirements in a system that includes an application circuit, the apparatus comprising:
An apparatus for reducing power requirements in a system that includes an application circuit, the apparatus comprising:
A method for reducing power requirements in a system that includes an application circuit, the method comprising:
Dependencies are inferred from the claim text.