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US 6,806,570 B1Granted
Thermal compliant semiconductor chip wiring structure for chip scale packaging
AssigneeMegic Corporation
InventorsJin-Yuan Lee, Eric Lin
Life of this patent
Estimating the term…
Abstract
A thermally compliant multi-layer wiring structure on a semiconductor chip is described. The multi-layer wiring structure incorporates an “empty” or air gap under the interconnect wiring and does not allow any thermally induced strains to be transmitted to the interconnecting solder balls. This design is to be used in chip scale packaging applications where printed circuit technology is used as the next level of package.
Claims20
A semiconductor chip multi-layer wiring structure comprising:
- a wiring layer interconnecting semiconductor circuit terminals to output terminals;
- solder ball terminals on said wiring layer used to interconnect said semiconductor chip to a wiring substrate;
- and
- an “empty” or air gap underlying said wiring layer underlying said solder ball terminals;
- wherein said “empty” or air gap provides a low strength buffer layer for absorbing thermally induced stresses between said semiconductor chip and said wiring substrate.
2 more elements
A semiconductor chip multi-layer wiring structure comprising:
- a wiring layer interconnecting semiconductor circuit terminals to output terminals;
- and
- solder ball terminals on said wiring layer used to interconnect said semiconductor chip to a wiring substrate
- wherein said wiring layer has a perforated pattern forming an “empty” or air gap underlying said solder ball terminals wherein the circumferential area of the said “empty” or air gap is partially enclosed by said wiring layer and wherein said “empty” or air gap provides a low strength buffer layer for absorbing thermally induced stresses between said semiconductor chip and said wiring substrate.
1 more element
A semiconductor chip multi-layer wiring structure comprising:
- a plurality of interconnected semiconductor device structures having metal pads in a topmost layer;
- a dielectric layer overlying said metal pads having openings therein exposing said metal pads;
- a wiring layer connecting said metal pads to output terminals;
- solder ball terminals on said wiring layer used to interconnect said metal pads to a wiring substrate;
- and
- an “empty” or air gap underlying or within said wiring layer underlying said solder ball terminals
- wherein said “empty” or air gap provides a low strength buffer layer for absorbing thermally induced stresses between said semiconductor chip and said wiring substrate.
4 more elements
Dependencies are inferred from the claim text.