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US 6,806,556 B2Granted
Semiconductor wafer, method of manufacturing semiconductor wafer having bumps, semiconductor chip having bumps and method of manufacturing the same, semiconductor device, circuit board, and electronic equipment
AssigneeSeiko Epson Corporation
InventorHiroshi Ohara
Life of this patent
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Abstract
A semiconductor wafer includes a plurality of monolithic integrated circuits formed in a semiconductor crystal for realizing a function of a plurality of semiconductor chips; a plurality of pads formed in a plurality of first regions to be the plurality of semiconductor chips; and a conductor formed in a layer lower than the pads through a second region, which is located between two of the first regions, and electrically connecting at least two of the pads.
Claims3
A semiconductor wafer comprising:
- a plurality of monolithic integrated circuits formed in a semiconductor crystal for realizing a function of a plurality of semiconductor chips;
- a plurality of pads formed in a plurality of first regions to be the plurality of semiconductor chips;
- and
- a conductive film formed on the pads semiconductor wafer through a second region, which is located between two of the first regions, and electrically connecting at least two of the pads,
- wherein the conductive film has a first part and a plurality of second parts,
- wherein the first part is formed along and inside the second region so as to enclose each of the first regions, and
- wherein each of the second parts electrically connects a pair of the pads adjacent to each other across the second region, the second parts electrically connected with the first part, a part of each of the second parts formed on the pads.
4 more elements
Dependencies are inferred from the claim text.