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US 6,806,550 B2Granted
Evaluation configuration for semiconductor memories
AssigneeInfineon Technologies AG
InventorsKurt Hoffmann, Oskar Kowarik
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Abstract
An evaluation configuration has a first MOS evaluation stage, an isolation stage, and a bipolar evaluation stage. The isolation stage is connected between the first MOS evaluation stage and the bipolar evaluation stage. The isolation stage isolates the first MOS evaluation stage from the bipolar evaluation stage. The evaluation configuration can reliably detect very small read signals and allows a high integration density.
Claims11
An evaluation configuration for semiconductor memories, the evaluation configuration comprising:
- a first MOS evaluation stage;
- a second bipolar evaluation stage;
- and
- an isolation stage connected between said first MOS evaluation stage and said second bipolar evaluation stage, said isolation stage isolating said second bipolar evaluation stage from said first MOS evaluation stage.
1 more element
Dependencies are inferred from the claim text.