Damascene method for improved MOS transistor

Method for fabricating a high performance MOSFET device having a novel gate structure comprising the steps of:

• a) providing a structure of at least one pad layers to function as a mandrel over a semiconductor substrate, said one or more pad layers having an aperture;
• b) depositing a high density plasma dielectric material within said aperture;
• c) forming respective spacer elements on either sidewall of said aperture overlying said high density plasma dielectric material in said aperture;
• d) removing a portion of said high density plasma dielectric material not underlying said spacer elements within said aperture, forming high density plasma dielectric placeholders defining a region of sub-lithographic width;
• e) forming a gate dielectric in said region, wherein said gate dielectric is positioned between said high density plasma dielectric placeholders;
• f) forming a first gate conductor material in said region to form a sub-lithographic lower gate conducting portion within said aperture;
• g) depositing a second gate conductor material to form an upper gate conducting portion within said aperture having a dimension that is wider than said sub-lithographic lower gate conducting portion, and self-aligned to said sub-lithographic lower gate conductor portion;
• wherein a resulting MOSFET device includes a sub-lithographic channel length according to said sub-lithographic lower gate conducting portion.