Semiconductor device and operation method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsYuji Takeuchi, Riichiro Shirota
Life of this patent
Estimating the term…
Abstract
A semiconductor device with a non-volatile memory, having: first to fourth memory cells arranged in a first direction; a first bit line extending over the first memory cell in a second direction and connected to the second memory cell; a second bit line extending over the second memory cell in the second direction and connected to the first memory cell; a third bit line extending over the third memory cell in the second direction and connected to the third memory cell; and a fourth bit line extending over the fourth memory cell in the second direction and connected to the fourth memory cell.
Claims16
A semiconductor device including a non-volatile memory, comprising:
- first, second, third and fourth memory cells arranged adjacent to each other in an order from the first memory cell to the fourth memory cell in a first direction;
- first, second, third and fourth bit lines arranged adjacent to each other in an order from the first bit line to the fourth bit line in a first direction;
- wherein,
- the first bit line extends over the first memory cell in a second direction and is connected to the second memory cell;
- the second bit line extends over said second memory cell in said second direction and is connected to said first memory cell;
- the third bit line extends over said third memory cell in said second direction and is connected to said third memory cell;
- and
- the fourth bit line extends over said fourth memory cell in said second direction and is connected to said fourth memory cell,
- wherein gate electrodes of the first, second, third, and fourth memory cells are each connected to a first word line.
A semiconductor device with a non-volatile memory, comprising:
- first, second, third and fourth bit lines arranged in a first direction and extending in a second direction;
- and
- memory cell units including a plurality of memory cells which are provided under said first, second, third and fourth bit lines and are arranged in a second direction,
- wherein:
- said memory cells of (4n (“n” is a natural number))th and (4n+1)th memory cell unit, which is arranged in the second direction and is positioned under said first bit line, are connected to said second bit line;
- said memory cells of (4n)th and (4n+1)th memory cell unit, which is arranged in the second direction and are positioned under said second bit line, are connected to said first bit line;
- said memory cells of(4n+2)th and (4n+3)th memory cell units, which are arranged in the second direction and are positioned under said third bit line, are connected to said third bit line;
- and said memory cells of (4n+2)th and (4n+3)th memory cell units, which are arranged in the second direction and is positioned under said fourth bit line, are connected to said fourth bit line.
A semiconductor device with a non-volatile memory, comprising:
- (4N (“N” is a natural number))th, (4N+1)th, (4N+2)th, (4N+3)th and (4N+4)th bit lines arranged in a first direction and extending in a second direction;
- memory cell units including a plurality of memory cells which are provided under said (4N)th, (4N+1)th, (4N+2)th and (4N+3)th bit lines and arranged in a second direction,
- wherein:
- said memory cells of(8n (“n” is a natural number))th and (8n+1)th memory cell unit, which is arranged in the second direction and is positioned under said (4N)th bit line, are connected to said (4N+1)th bit line;
- said memory cells of (8n)th and (8n+1)th memory cell unit, which is arranged in the second direction and is positioned under said (4N+1)th bit line, are connected to said (4N)th bit line;
- said memory cells of (8n+2)th and (8n+3)th memory cell units, which are arranged in the second direction and are positioned under said (4N+1)th bit line, are connected to said (4N+2)th bit line;
- said memory cells of (8n+2)th and (8n+3)th memory cell units, which are arranged in the second direction and are positioned under said (4N+2)th bit line, are connected to said (4N+1)th bit line;
- said memory cells of (8n+4)th and (8n+5)th memory cell units, which are arranged in the second direction and are positioned under said (4N+2)th bit line, are connected to said (4N+3)th bit line;
- said memory cells of (8n+4)th and (8n+5)th memory cell units, which are arranged in the second direction and are positioned under said (4N+3)th bit line, are connected to said (4N+2)th bit line;
- said memory cells of (8n+6)th and (8n+7)th memory cell units, which are arranged in the second direction and are positioned under said (4N+3)th bit line, are connected to said (4N+4)th bit line;
- and said memory cells of (8n+6)th and (8n+7)th memory cell units, which are arranged in the second direction and are positioned under said (4N+4)th bit line, are connected to said (4N+3)th bit line.
An operation method of a semiconductor device including a non-volatile memory, which comprises first, second, third and fourth memory cells arranged adjacent to each other in an order from the first memory cell to the fourth memory cell in a first direction;
- first, second, third and fourth bit lines arranged adjacent to each other in an order from the first bit line to the fourth bit line in a first direction;
- wherein, the first bit line extends over said first memory cell in a second direction and is connected to said second memory cell, the second bit line extends over said second memory cell in said second direction and is connected to said first memory cell, the third bit line extends over said third memory cell in said second direction and is connected to said third memory cell, and the fourth bit line extends over said fourth memory cell in said second direction and is connected to said fourth memory cell,
- the operation method comprising:
- writing data into said second and third memory cells connected to said first and third bit lines;
- verifying the data written in said second and third memory cells;
- writing data into said first and fourth memory cells connected to said second and fourth bit lines;
- and
- verifying data written in said first and fourth memory cells.
An operation method of a semiconductor device which includes a non-volatile memory in which a plurality of memory cells are connected to bit lines and word lines, are arranged in the shape of a matrix and are capable of having positive ternary or more data “m” written therein,
- the operation method comprising:
- initializing all of said memory cells;
- and
- writing data into said memory cells m-1 times, wherein data written after the initialization are sequentially added to the data written during the initialization.
Dependencies are inferred from the claim text.