Integrated high performance MOS tunneling LED in ULSI technology

A method of creating Metal Oxide Semiconductor (MOS) devices and of creating Light Emitting Diode (LED) devices over a substrate, comprising the steps of:

• providing a substrate, a first surface area of said substrate having been designated as being a surface area over which CMOS devices are to be created, a second surface area of said substrate having been designated as being a surface area over which MOS tunneling LED devices are to be created;
• performing a first process of oxidation of said substrate, thereby creating a first layer of gate oxide having a first thickness overlying said first surface area of said substrate, further creating a second layer of gate oxide having a second thickness overlying said second surface region of said substrate;
• providing an etch resist mask over said first layer of gate oxide, shielding said first layer of gate oxide, exposing said second layer of gate oxide;
• performing a plasma etch to the exposed surface of said second layer of gate oxide, creating a third layer of gate oxide having a third thickness overlying said second surface region of said substrate;
• removing said etch resist mask from said first layer of gate oxide, exposing said first layer of gate oxide;
• performing a second process of oxidation of said first layer of gate oxide and of said third layer of gate oxide, creating a fourth layer of gate oxide having a fourth thickness over said substrate overlying said first surface area of said substrate, further creating a fifth layer of gate oxide having a fifth thickness over said substrate overlying said second surface area of said substrate.

A structure of Metal Oxide Semiconductor (MOS) tunneling Light Emitting Diode (LED) devices integrated into Ultra Large Scale Integrated devices, comprising:

• a substrate, the substrate comprising a first surface area over which CMOS devices are to be created, the substrate further comprising a second surface over which LED devices are to be created;
• layers of gate oxide, comprising:
• (1) overlying said second surface area a second layer of gate oxide having a second thickness, comprising:
• (i) a plasma exposed lower layer of gate oxide;
• and
• (ii) an upper layer of gate oxide over the plasma exposed lower layer of gate oxide;
• and
• (2) overlying said first surface area a first layer of gate oxide having a first thickness, said first thickness being larger than said second thickness.