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US 6,806,494 B2Granted
Method and apparatus for wafer-level burn-in and testing of integrated circuits
AssigneeMedtronic, Inc.
InventorsAndreas A. Fenner, David L. Thompson
Life of this patent
Estimating the term…
Abstract
In one embodiment, a testing regimen is implemented to reduce test time. Specifically, a structure and method to power up and stabilize all die on the wafer prior to testing each die is implemented. More specifically, parallel powering schemes including die stabilization procedures are used to ready the wafer for testing. A wafer probe tester is indexed from one die to the next for an uninterrupted testing of all die in the wafer subsequent to all die power up and stabilization.
Claims9
A method of inspecting a burn-in testing result of a plurality of dies, comprising:
- coupling an external power supply to at least one conductive pad disposed in an inactive region of a semiconductor wafer;
- and
- inspecting each of a plurality of burn-in indicating apparatuses, wherein each of said plurality of burn-in indicating apparatuses is coupled to a corresponding one die of a plurality of dies and is disposed on an active region of said semiconductor wafer, to determine whether a burn-in parameter has been satisfied.
Dependencies are inferred from the claim text.