Heterojunction organic semiconductor field effect transistor (FET) with a gate insulation layer and manufacturing process thereof
AssigneeChangchun Institute of Applied Chemistry Chinese Academy of Science
InventorsDonghang Yan, Jian Zhang, Jun Wang, Haibo Wang, Xuanjun Yan
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Abstract
A organic semiconductor field effect transistor that can work in the depletion mode or super-inverse mode, comprising: a substrate (1), a gate electrode (2) formed on the substrate (1), a gate insulation layer (3) formed on the substrate (1) and the gate electrode (2), a first semiconductor layer (4) formed on the gate insulation layer (3), a source electrode and a drain electrode (5) formed on the first semiconductor layer (4), and a second semiconductor layer (6) formed on the first semiconductor layer (4) and the source/drain electrodes (5).
Claims9
A heterojunction organic semiconductor field effect transistor, comprising:
- a substrate (1),
- a gate electrode (2) formed on the substrate (1),
- a gate insulation layer (3) formed on the substrate (1) and the gate electrode (2),
- a first semiconductor layer (4) formed on the gate insulation layer (3),
- a source/drain electrode (5) formed on the first semiconductor layer (4), and
- a second semiconductor layer (6) formed on the first semiconductor layer (4) and the source/drain electrode (5).
A process for manufacturing a organic semiconductor field effect transistor containing a heterojunction, comprising the following steps:
- Step a. forming a gate electrode on a substrate;
- Step b. forming an insulation layer on the substrate and the gate electrode;
- Step c. forming a first semiconductor layer on the insulation layer formed in Step b;
- Step d. forming a source electrode and a drain electrode on the first semiconductor layer;
- Step e. forming a second semiconductor layer on the source electrode, the drain electrode and the first semiconductor layer.
A process for manufacturing a organic semiconductor field effect transistor containing a heterojunction, comprising the following steps:
- Step a. forming a first semiconductor layer on a substrate;
- Step b. forming a source electrode and a drain electrode on the first semiconductor layer;
- Step c. forming a second semiconductor layer on the first semiconductor layer, the source electrode and the drain electrode;
- Step d. forming an insulation layer on the second semiconductor layer;
- and
- Step e. forming a gate electrode on the insulation layer formed in Step d.
Dependencies are inferred from the claim text.