Method of manufacturing a field effect transistor

A method of manufacturing a field effect transistor comprising:

• forming an active region in a substrate;
• forming a gate electrode over said substrate, said gate electrode being electrically insulated from said substrate by a gate insulation layer;
• forming a first amorphized region and a second amorphized region in said substrate adjacent to said gate electrode by implanting ions of a non-doping element;
• forming a doped extended source region in said first amorphized region and a doped extended drain region in said second amorphized region by implanting ions of a first dopant, wherein said first and second amorphized regions are formed to a depth that is greater than a death of said source and drain regions;
• forming a first dielectric sidewall spacer and a second dielectric sidewall pacer adjacent to said gate electrode;
• forming a doped source region adjacent to said first sidewall spacer and a doped drain region adjacent to said second sidewall spacer by implanting ions of a second dopant;
• and
• annealing said substrate, said annealing leading to solid phase epitaxial regrowth of said first and second amorphized regions and to an activation of said first and second dopants.

A method of manufacturing a field effect transistor, comprising:

• forming an active region in a substrate;
• forming a gate electrode over said substrate, said gate electrode being electrically insulated from said substrate by a gate insulation layer;
• forming a doped extended source region and a doped extended drain region in said substrate adjacent to said gate electrode by implanting ions of a first dopant;
• forming a first dielectric sidewall spacer and a second dielectric sidewall spacer adjacent to said gate electrode;
• forming a doped source region in said substrate adjacent to said first sidewall spacer and a doped drain region in said substrate adjacent to said second sidewall spacer by implanting ions of a second dopant;
• forming a first amorphized region comprising said extended source region and a second amorphized region comprising said extended drain region in said substrate by implanting ions of a non-doping element, wherein said first and second amorphized regions are formed to a depth that is greater than a depth of said source and drain regions;
• and
• annealing said substrate, said annealing leading to solid phase epitaxial regrowth of said first and second amorphized regions, and to an activation of said first and second dopants.

A method of manufacturing a field effect transistor comprised of source and drain regions having a dopant material positioned therein, the method comprising:

• forming amorphized regions in an active region in a substrate by implanting ions of a non-doping element, wherein said amorphized regions are formed prior to performing any anneal process to activate said dopant material in said source and drain regions, and wherein said amorphized regions are formed to a depth that is greater than a depth of said source and drain regions;
• forming said source and drain regions with a specified lateral and depth profile;
• and
• performing a solid phase epitaxial regrowth of said amorphized regions at a temperature substantially maintaining said specified lateral and depth profile.

A method of manufacturing a field effect transistor comprised of source and drain regions having a dopant material positioned therein, the method comprising:

• forming an active region in a substrate;
• forming a gate electrode over said substrate, said gate electrode being electrically insulated from said substrate by a gate insulation layer;
• forming a first amorphized region and a second amorphized region in said substrate adjacent to said gate electrode by implanting ions of a non-doping element, wherein said first and second amorphized regions are formed prior to performing any anneal process to activate said dopant material in said source and drain regions, and wherein said first and second amorphized regions formed to a depth that is greater than a depth of said source and drain regions;
• forming a doped extended source region in said first amorphized region and a doped extended drain region in said second amorphized region by implanting ions of a first dopant;
• forming a first dielectric sidewall spacer and a second dielectric sidewall spacer adjacent to said gate electrode;
• forming a doped source region adjacent to said first sidewall spacer and doped drain region adjacent to said second sidewall spacer by implanting ions of a second dopant;
• and
• annealing said substrate, said annealing leading to solid phase epitaxial regrowth of said first and second amorphized regions and to an activation of said first and second dopants.

A method of manufacturing a field effect transistor comprised of source and drain regions having a dopant material positioned therein, the method comprising:

• forming an active region in a substrate;
• forming a gate electrode over said substrate, said gate electrode being electrically insulated from said substrate by a gate insulation layer;
• forming a doped extended source region and a doped extended drain region in said substrate adjacent to said gate electrode by implanting ions of a first dopant;
• forming a first dielectric sidewall spacer and a second dielectric sidewall spacer adjacent to said gate electrode;
• forming a doped source region in said substrate adjacent to said first sidewall spacer and a doped drain region in said substrate adjacent to said second sidewall spacer by implanting ions of a second dopant;
• forming a first amorphized region comprising said extended source region and a second amorphized region comprising said extended drain region in said substrate by implanting ions of a non-doping element, wherein said first and second amorphized regions are formed prior to performing any anneal process to activate said dopant material in said source and drain regions, and wherein said first and second amorphized regions are formed to a depth that is greater than a depth of said source and drain regions;
• and
• annealing said substrate, said annealing leading to solid phase epitaxial regrowth of said first and second amorphized regions, and to an activation of said first and second dopants.

A method of manufacturing a field effect transistor, comprising:

• forming an active region in a substrate;
• forming a gate electrode over said substrate, said gate electrode being electrically insulated from said substrate by a gate insulation layer;
• forming a doped extended source region and a doped extended drain region in said substrate adjacent to said gate electrode by implanting ions of a first dopant;
• forming a first dielectric sidewall spacer and a second dielectric sidewall pacer adjacent to said gate electrode;
• forming a doped source region in said substrate adjacent to said first sidewall spacer and a doped drain region in said substrate adjacent to said second sidewall spacer by implanting ions of a second dopant;
• forming a first amorphized region comprising said extended source region and a second amorphized region comprising said extended drain region in said substrate by implanting ions of a non-doping element, wherein said first and second amorphized regions are formed to a depth that is greater than a depth of said source and drain regions;
• annealing said substrate, said annealing leading to solid phase epitaxial regrowth of said first and second amorphized regions, and to an activation of said first and second dopants;
• forming a third amorphized region comprising said source region and a fourth amorphized region comprising said drain region in said substrate;
• and
• removing said first sidewall spacer and said second sidewall spacer;
• wherein said formation of said third and fourth amorphized regions and said removing of said first and second sidewall spacers are performed before said formation of said first and second amorphized regions.

A method of manufacturing a field effect transistor comprised of source and drain regions having a dopant material positioned therein, the method comprising:

• forming an active region in a substrate;
• forming a gate electrode over said substrate, said gate electrode being electrically insulated from said substrate by a gate insulation layer;
• forming a doped extended source region and a doped extended drain region in said substrate adjacent to said gate electrode by implanting ions of a first dopant;
• forming a first dielectric sidewall spacer and a second dielectric sidewall spacer adjacent to said gate electrode;
• forming a doped source region in said substrate adjacent to said first sidewall spacer and a doped drain region in said substrate adjacent to said second sidewall spacer by implanting ions of a second dopant;
• forming a first amorphized region comprising said extended source region and a second amorphized region comprising said extended drain region in said substrate by implanting ions of a non-doping element, wherein said first and second amorphized regions are formed prior to performing any anneal process to activate said dopant material in said source and drain regions, and wherein said first and second amorphized regions are formed to a depth that is greater than a depth of said source and drain regions;
• annealing said substrate, said annealing leading to solid phase epitaxial growth of said first and second amorphized regions, and to an activation of said first and second dopants;
• forming a third amorphized region comprising said source region and a fourth amorphized region comprising said drain region in said substrate;
• and
• removing said first sidewall spacer and said second sidewall spacer,
• wherein said formation of said third and fourth amorphized regions and said removing of said first and second sidewall spacers are performed before said formation of said first and second amorphized regions.