Methods of manufacturing semiconductor memory devices with epitaxial contact nodes

A method of fabricating a semiconductor memory device, the method comprising:

• forming an isolation layer on a semiconductor substrate and forming a capping layer on the isolation layer;
• forming an epitaxial active region, which is not covered with the isolation layer, on said semiconductor substrate by selective epitaxial growth;
• forming a gate insulation layer and a gate electrode on said epitaxial active region, sequentially;
• forming a bit line contact plug and a storage node contact plug spaced apart from the both sides of said gate electrode on said semiconductor substrate by epitaxially growing, respectively;
• forming a source/drain into said epitaxial active region on which said bit line contact plug and said storage node contact plug are formed;
• forming a lower interlayer insulation layer on the entire surface of the resultant structure and planarizing the lower interlayer insulation layer to expose a top surface of said bit line contact plug and said storage node contact plug;
• forming an upper interlayer insulation layer on the entire surface of the resultant structure after said lower interlayer insulation layer is planarized and forming a bit line in the upper interlayer insulation layer, wherein the bit line is connected to the bit line contact plug;
• forming an additional upper interlayer insulation layer on the resultant structure;
• forming a storage node electrode connected to said storage node contact plug through said additional upper interlayer insulation layer and said upper interlayer insulation layer;
• and
• forming a dielectric layer and a plate node electrode on the entire surface of the resultant structure, sequentially.