Field effect transistor with gate layer and method of making same

A method for forming a field effect transistor comprising the steps of:

• a) providing a substrate of semiconductor material;
• then
• b) etching said substrate to form an upstanding pillar adjacent a substantially-planar upper surface of said etched substrate;
• then
• c) creating a conductively-doped region within said etched substrate substantially and immediately beneath said pillar;
• then
• d) forming a stack of substantially-planar layers of material adjacent said pillar, said stack of materials comprising a first insulator layer adjacent said upper surface of said etched substrate, a gate layer of conductive material overlying said first insulator layer and a second insulator layer overlying said gate layer;
• then
• e) etching said pillar to the level of said substantially-planar upper surface of said etched substrate to form an upstanding pore within said stack;
• then
• f) forming a gate insulator layer interior to said upstanding pore;
• then
• g) forming an upstanding channel of semiconductor material having a top region and a bottom region interior of said gate insulator layer;
• and then
• h) heavily doping said top region of said upstanding channel.

A method for forming a field effect transistor comprising the steps of:

• a) providing a substrate having an upper surface;
• then
• b) forming a stack of substantially-planar layers of material on said substrate, said stack comprising a first insulator layer adjacent said upper surface of said substrate, a gate layer of conductive material overlying said first insulator layer and a second insulator layer overlying said gate layer;
• then
• c) forming an overlayer on top of said second insulator layer;
• then
• d) masking said overlayer with a nanoparticle;
• then
• e) directionally etching said overlayer to form an upstanding nanopillar on top of said second insulator layer;
• then
• f) depositing a second overlayer on top of said second insulator layer and said upstanding nanopillar;
• then
• g) removing said second overlayer to the top of said upstanding nanopillar;
• then
• h) removing said nanopillar to leave an upper nanopore within said second overlayer defining an etch mask;
• then
• i) directionally etching a lower nanopore to said upper surface of said substrate;
• then
• j) removing said second overlayer;
• then
• k) forming a gate insulator layer at the interior of said upstanding nanopore;
• then
• l) forming an upstanding channel of semiconductor material having a top region and a bottom region interior of said gate insulator layer;
• and then
• m) heavily doping said top region of said upstanding channel of semiconductor material.