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US 6,806,136 B1Granted
Method of forming a semiconductor device having a capacitor and a resistor
AssigneeEpisil Technologies Inc.
InventorHsiu-Wen Hsu
Life of this patent
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Abstract
The present invention relates generally to semiconductor fabrication and more specifically to simultaneous formation of capacitors, resistors and metal oxide semiconductor.
Claims31
A method of simultaneously forming at least one capacitor, at least two resistors and at least one metal-oxide semiconductor, comprising the steps of:
- providing a structure having an exposed oxide structure;
- the structure having a capacitor region within at least a portion of the exposed oxide structure;
- a first resistor region within at least a portion of the exposed oxide structure;
- a second resistor region within at least a portion of the exposed oxide structure;
- and a metal-oxide semiconductor region not within at least a portion of the exposed oxide structure;
- forming a first polysilicon layer over the structure and the exposed oxide structure;
- doping the first polysilicon layer to form a doped first polysilicon layer;
- forming an interpoly oxide film over the doped first polysilicon layer;
- patterning the interpoly oxide film to form:
- a capacitor interpoly oxide film portion within the capacitor region over the oxide structure;
- and
- a second interpoly oxide film portion within the second resistor region over the oxide structure;
- forming a second polysilicon layer over the structure;
- doping the second polysilicon layer to form a doped second polysilicon layer;
- and
- patterning the doped second polysilicon layer and the doped first polysilicon layer to simultaneously form:
- within the capacitor region:
- a lower capacitor doped first polysilicon portion underneath at least a portion of the capacitor interpoly oxide film portion, and an overlying upper capacitor second doped polysilicon portion over at least a portion of the patterned capacitor interpoly oxide film portion;
- within the first resistor region:
- a lower first resistor first polysilicon portion and an upper, overlying first resistor second polysilicon portion;
- within the second resistor region:
- a lower second resistor first polysilicon portion underneath at least a portion of the second interpoly oxide film portion;
- and
- within the metal-oxide semiconductor region:
- a lower metal-oxide semiconductor first polysilicon portion and an overlying metal-oxide semiconductor second polysilicon portion.
22 more elements
A method of simultaneously forming at least one capacitor, at least two resistors and at least one metal-oxide semiconductor, comprising the steps of:
- providing a substrate having an exposed oxide structure;
- the exposed oxide structure being a field oxide film;
- the substrate having a capacitor region within at least a portion of the exposed oxide structure;
- a first resistor region within at least a portion of the exposed oxide structure;
- a second resistor region within at least a portion of the exposed oxide structure;
- and a metal-oxide semiconductor region not within at least a portion of the exposed oxide structure;
- forming a first polysilicon layer over the substrate and the exposed oxide structure;
- doping the first polysilicon layer to form a doped first polysilicon layer;
- forming an interpoly oxide film over the doped first polysilicon layer;
- patterning the interpoly oxide film to form:
- a capacitor interpoly oxide film portion within the capacitor region over the oxide structure;
- and
- a second interpoly oxide film portion within the second resistor region over the oxide structure;
- forming a second polysilicon layer over the substrate;
- doping the second polysilicon layer to form a doped second polysilicon layer;
- and
- patterning the doped second polysilicon layer and the doped first polysilicon layer to simultaneously form:
- within the capacitor region:
- a lower capacitor doped first polysilicon portion underneath at least a portion of the capacitor interpoly oxide film portion, and an overlying upper capacitor second doped polysilicon portion over at least a portion of the patterned capacitor interpoly oxide film portion;
- within the first resistor region:
- a lower first resistor first polysilicon portion and an upper, overlying first resistor second polysilicon portion;
- within the second resistor region:
- a lower second resistor first polysilicon portion underneath at least a portion of the second interpoly oxide film portion;
- and
- within the metal-oxide semiconductor region:
- a lower metal-oxide semiconductor first polysilicon portion and an overlying metal-oxide semiconductor second polysilicon portion.
23 more elements
A method of simultaneously forming at least one capacitor, at least two resistors and at least one metal-oxide semiconductor, comprising the steps of:
- providing a structure having an exposed oxide structure having a thickness of from about 4000 to 7500 Å;
- the structure having a capacitor region within at least a portion of the exposed oxide structure;
- a first resistor region within at least a portion of the exposed oxide structure;
- a second resistor region within at least a portion of the exposed oxide structure;
- and a metal-oxide semiconductor region not within at least a portion of the exposed oxide structure;
- forming a first polysilicon layer over the structure and the exposed oxide structure;
- the first polysilicon layer having a thickness of from about 1000 to 2500 Å;
- doping the first polysilicon layer to form a doped first polysilicon layer;
- forming an interpoly oxide film over the doped first polysilicon layer;
- the interpoly film having a thickness of from about 250 to 600 Å;
- patterning the interpoly oxide film to form:
- a capacitor interpoly oxide film portion within the capacitor region over the oxide structure;
- and
- a second interpoly oxide film portion within the second resistor region over the oxide structure;
- forming a second polysilicon layer over the structure;
- the second polysilicon layer having a thickness of from about 1000 to 2500 Å;
- doping the second polysilicon layer to form a doped second polysilicon layer;
- and
- patterning the doped second polysilicon layer and the doped first polysilicon layer to simultaneously form:
- within the capacitor region:
- a lower capacitor doped first polysilicon portion underneath at least a portion of the capacitor interpoly oxide film portion, and an overlying upper capacitor second doped polysilicon portion over at least a portion of the patterned capacitor interpoly oxide film portion;
- within the first resistor region:
- a lower first resistor first polysilicon portion and an upper, overlying first resistor second polysilicon portion;
- within the second resistor region:
- a lower second resistor first polysilicon portion underneath at least a portion of the second interpoly oxide film portion;
- and
- within the metal-oxide semiconductor region:
- a lower metal-oxide semiconductor first polysilicon portion and an overlying metal-oxide semiconductor second polysilicon portion.
25 more elements
Dependencies are inferred from the claim text.