US 6,806,131 B2Granted

Process for manufacturing a DMOS transistor

AssigneeATMEL Germany GmbH

InventorsChristoph Bromberger, Franz Dietz, Volker Dudek, Michael Graf, Joern Herrfurth, Manfred Klaussner

Life of this patent

Estimating the term…

Loading patent…

Abstract

In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.

Claims48

Dependent claims

A process for manufacturing a DMOS transistor (100) with a semiconductor body (5), which features a surface layer with a source region (10) and a drain region (80) of a second conductivity type, and a first well region (20) of a first conductivity type enclosing the source region (10), and a second well region (19) of a second conductivity type enclosing the drain region, wherein the first well region (20) and the second well region (19) are separated by a body region (18) of a first conductivity type, and a gate region (35) is formed on the surface of the surface layer of the semiconductor body (5), which gate region extends from the source region across the first well region (20),

said method comprising:
starting on the surface of the semiconductor body (5), forming a trench-shaped structure in the surface layer, such that the trench-shaped structure includes a floor region, source-end side wall extending from the floor region to the surface on a first side of the trench-shaped structure proximate to the source region, and a drain-end side wall on a second side of the trench-shaped structure proximate to the drain region, wherein at least one of the side walls slopes non-perpendicularly relative to the surface so that the trench-shaped structure has a tapering cross-section with a greater width at the surface than at the floor region;
producing a doping of the second conductivity type with a first concentration value in the floor region of the trench-shaped structure;
producing a doping of the second conductivity type with a second concentration value in the source-end side wall of the trench-shaped structure;
producing a doping of the second conductivity type with a third concentration value in the drain-end side wall of the trench-shaped structure;
and
forming, in the surface layer, the source region and the drain region of the second conductivity type, the first well region of the first conductivity type enclosing the source region, and the second well region of the second conductivity type enclosing the drain region, with the body region of the first conductivity type being between and separating the first and second well regions, and forming the gate region the surface of the surface layer so that the gate region extends from the source region over the first well region.

4 more elements

A process of manufacturing a DMOS transistor, comprising the steps:

a) providing a semiconductor body having a surface;
b) etching a trench into said semiconductor body from said surface, so that said trench is bounded by a floor and first and second side walls extending from said surface to said floor, wherein said first and second side walls are non-parallel relative to each other and said trench has a tapering cross-section with a greater width between said first and a second side walls at said surface than at said floor;
c) implanting a dopant into said semiconductor body to result in a first dopant concentration of said dopant in a first wall region of said semiconductor body along a location of said first side wall, a second dopant concentration of said dopant in a second wall region of said semiconductor body along a location of said second side wall, and a third dopant concentration of said dopant in a floor region of said semiconductor body along a location of said floor;
d) forming in said semiconductor body a source region adjacent to said location of said first side wall;
e) forming in said semiconductor body a drain region adjacent to said location of said second side wall;
f) forming in said semiconductor body a first well region of a first conductivity type at a location underlying said source region;
g) forming in said semiconductor body a second well region of a second conductivity type at a location underlying said drain region;
h) forming in said semiconductor body a body region of said first conductivity type at a location between said first well region and said second well region;
and
i) forming a gate structure on said surface of said semiconductor body and adjoining said source region.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/167,960Filed 11 Jun 2002
Priority: DE 101 31 70729 Jun 2001
Published: US 2003/0003638 A12 Jan 2003
Granted: 19 Oct 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 62/159
Drain regions of DMOS transistors: shapes
H10D 30/0221
Of FETs having insulated gates [IGFET]: having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or…
H10D 30/0281
Of double-diffused metal oxide semiconductor [DMOS] FETs: of lateral dmos [ldmos] fets
H10D 30/603
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having asymmetry in the channel direction, e.g. lateral…