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US 6,806,128 B2Granted
Semiconductor integrated circuit device and a method of manufacturing the same
AssigneeRenesas Technology Corp.
InventorsFumio Ootsuka, Katsuhiko Ichinose, Shoji Wakahara
Life of this patent
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Abstract
With a gate electrode and side wall spacers being used as masks, ions of an n-type impurity are implanted from the normal line direction of a substrate, whereby source/drain diffused regions are formed. Then, ions of an n-type impurity are introduced by oblique implantation having a predetermined angle relative to the normal line direction of the substrate to form an n-type semiconductor region having an impurity concentration higher than source/drain extended regions. By this method, the junction depth of the semiconductor region becomes smaller than that of the source/drain diffused regions and greater than that of the source/drain extended regions.
Claims35
A method of manufacturing a semiconductor integrated circuit device, comprising steps of:
- (a) forming a gate electrode over a substrate;
- (b) implanting ions of a first n-type impurity in the substrate at both ends of said gate electrode, thereby forming source/drain extended regions;
- (c) forming side wall spacers on the side walls of said gate electrode;
- (d) implanting ions of a second n-type impurity in said substrate in self alignment with said gate electrode and said side wail spacers, to form source/drain diffused regions comprising a higher impurity concentration than said source/drain extended regions;
- (e) cleaning said substrate;
- and
- (f) depositing a refractory metal film over said substrate, and forming a silicide layer on a surface of said source/drain diffused regions by heat treatment, wherein said method further comprises, after said step (c), a step of implanting ions of a third n-type impurity into said substrate in self alignment with said gate electrode and said side wall spacers, to form a semiconductor region comprising a higher impurity concentration than said source/drain extended regions, and
- wherein said source/drain extended regions, said semiconductor region, said silicide layer, and said source/drain diffused regions are arranged in the order of mention from a channel region toward the end portion of said side wall spacers in the substrate.
5 more elements
A method of manufacturing a semiconductor integrated circuit device, comprising steps of:
- (a) forming a gate electrode over a substrate;
- (b) introducing an impurity in said substrate in self alignment with said gate electrode for forming source/drain extended regions;
- (c) forming side wall spacers on side surfaces of said gate electrode;
- (d) introducing an impurity in said substrate in self alignment with said side wall spacers for forming source/drain diffused regions;
- (e) introducing an impurity into said substrate in self alignment with said gate electrode and said side wall spacers by oblique implantation at a predetermined inclination relative to a normal line of said substrate for forming semiconductor regions having the same conductivity type of said source/drain diffused regions and source/drain extended regions;
- (f) after said steps (d) and (a), cleaning said substrate and depositing a refractory metal film over said substrate for forming silicide layers on a surface of said source/drain diffused regions by heat treatment,
- wherein said source/drain extended regions, said semiconductor regions and said source/drain diffused regions are arranged in the order of mention from a channel region to the end portion of said side wall spacers in the substrate,
- wherein a junction depth of each of said semiconductor regions is greater than that of said source/drain extended regions but smaller than that of said source/drain diffused regions, and
- wherein an impurity concentration of said source/drain extended regions is lower than that of said semiconductor regions and said source/drain diffused regions.
6 more elements
A method of manufacturing a semiconductor integrated circuit device, comprising steps of:
- (a) introducing an impurity in a substrate in self alignment with a gate electrode for forming source/drain extended regions;
- (b) forming side wall spacers on side surfaces of said gate electrode;
- (c) introducing an impurity in said substrate in self alignment with said side wall spacers for forming source/drain diffused regions;
- (d) introducing an impurity into said substrate in self alignment with said gate electrode and said side wall spacers for forming a semiconductor regions having the same conductivity type of said source/drain diffused regions and source/drain extended regions;
- and
- (e) after said steps (c) and (d), cleaning said substrate and depositing a refractory metal film over said substrate for forming silicide layers on a surface of said source/drain diffused regions by heat treatment,
- wherein before said steps (c) and (d), a selective epitaxial layer is formed on regions of said substrate not covered by said side wall spacers,
- wherein said source/drain extended regions, said semiconductor regions and said source/drain diffused regions are arranged in the order of mention from a channel region to the end portion of said side wall spacers in the substrate,
- wherein a junction depth of each of said semiconductor regions is greater than that of said source/drain extended regions and smaller than that of said source/drain diffused regions, and
- wherein an impurity concentration of said source/drain extended regions is lower than that of said semiconductor regions and said source/drain diffused regions.
7 more elements
A method of manufacturing a semiconductor integrated circuit device, comprising steps of
- (a) forming a gate electrode over a substrate;
- (b) introducing an impurity in said substrate in self alignment with said gate electrode for forming source/drain extended regions;
- (c) forming side wall spacers on side surfaces of said gate electrode;
- (d) introducing an impurity into said substrate in self alignment with said side wall spacers for forming source/drain diffused regions;
- (e) introducing an impurity into said substrate in self alignment with said gate electrode and said side wall spacers by oblique implantation at a predetermined inclination relative to a normal line of said substrate for forming semiconductor regions having the same conductivity type of said source/drain diffused regions and said source/drain extended regions;
- (f) after said step (e), cleaning said substrate;
- (g) depositing a refractory metal film over said substrate, and forming a silicide layer on at least a surface of said source/drain diffused regions by heat treatment,
- wherein said source/drain extended regions, at least one of said semiconductor regions and said source/drain diffused regions are arranged in the order of mention from a channel region to the end portion of said side wall spacers in the substrate, and
- wherein an impurity concentration of said source/drain extended regions is lower than that of said semiconductor regions and said source/drain diffused regions.
6 more elements
A method of manufacturing a semiconductor integrated circuit device, comprising steps of
- (a) forming a gate electrode over a substrate;
- (b) introducing an impurity in said substrate in self alignment with said gate electrode for forming source/drain extended regions;
- (c) forming side wall spacers on side surfaces of said gate electrode;
- (d) introducing an impurity into said substrate in self alignment with said side wall spacers for forming source/drain diffused regions;
- (e) introducing an impurity into said substrate in self alignment with said gate electrode and said side wall for forming semiconductor regions having the same conductivity type of said source/drain diffused regions and said source/drain extended regions;
- (f) after said step (e), cleaning said substrate;
- and
- (g) depositing a refractory metal film over said substrate for forming silicide layers on a surface of said source/drain diffused regions by heat treatment,
- wherein at said step (e), said impurity is introduced in said substrate by oblique implantation at a predetermined inclination relative to a normal line of said substrate so that the end portion of said semiconductor regions is disposed between the end portion of said source/drain diffused regions and the end portion of said source/drain extended regions,
- wherein said semiconductor regions surround at least a portion of one of said silicide layers on a surface of said source/drain diffused regions, and
- wherein an impurity concentration of said source/drain extended regions is lower than that of said semiconductor regions and said source/drain diffused regions.
8 more elements
Dependencies are inferred from the claim text.