US 6,806,126 B1 · Method of manufacturing a semiconductor component

Abstract

An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

Claims25

Dependent claims

A method for manufacturing a semiconductor component, comprising:

providing a semiconductor material of a first conductivity type having a major surface;
forming a gate structure on the major surface, the gate structure having first and second sides and a top surface;
forming first and second spacers adjacent the first and second sides of the gate structure, respectively, the first and second spacers comprising a first dielectric material;
forming source and drain extension regions in the semiconductor material, the source extension region aligned to the first spacer and the drain extension region aligned to the second spacer;
forming third and fourth spacers adjacent the first and second spacers, respectively, the third and fourth spacers comprising the first dielectric material;
exposing portions of the first and second sides of the gate structure;
and
forming source and drain regions in the semiconductor material, the source region aligned to the third spacer and the drain region aligned to the fourth spacer.

5 more elements

Dependencies are inferred from the claim text.

Method of manufacturing a semiconductor component

Life of this patent

Method of manufacturing a semiconductor component

Life of this patent

Abstract

Claims25