US 6,806,123 B2Granted

Methods of forming isolation regions associated with semiconductor constructions

AssigneeMicron Technology, Inc.

InventorsMark McQueen, Luan C. Tran, Chandra Mouli

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Abstract

The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative material. The first material is doped to at least 1×1017 atoms/cm3 with n-type and p-type dopant. The invention also includes a semiconductor construction in which a doped material is over a segment of a substrate. The doped material has a first type majority dopant therein, and is electrically connected with an electrical ground. A pair of conductively-doped diffusion regions are adjacent the segment, and spaced from one another by at least a portion of the segment. The conductively-doped diffusion regions have a second type majority dopant therein. The invention also encompasses methods of forming semiconductor constructions.

Claims14

Dependent claims

A method of forming an isolation region associated with a semiconductor construction, comprising:

providing a construction comprising a semiconductor substrate, an insulative material over the substrate, and a semiconductive material over the insulative material;
masking a segment of the construction and leaving another segment of the construction unmasked, the masked segment defining an isolation region of the construction;
doping a portion of the semiconductor substrate of the unmasked segment;
and
etching the semiconductive material of the construction to form at least two transistor gates, wherein one of the two transistor gates is directly over the isolation region and comprises the semiconductive material of the masked segment, and wherein the other of the two transistor gates is directly over the doped semiconductor substrate and comprises the semiconductive material of the unmasked segment.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/133,193Filed 26 Apr 2002
Published: US 2003/0203564 A130 Oct 2003
Granted: 19 Oct 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 12/05
For one transistor one-capacitor [1T-1C] memory cells: making the transistor
H10B 12/09
Manufacture or treatment: with simultaneous manufacture of the peripheral circuit region and memory cells
H10B 12/48
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: data lines or contacts therefor
H10D 64/01326
Characterised by the conductor: aspects related to lithography, isolation or planarisation of the conductor