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US 6,806,117 B2Granted
Methods of testing/stressing a charge trapping device
AssigneeProgressant Technologies, Inc.
InventorTsu-Jae King
Life of this patent
Estimating the term…
Abstract
A method of testing/stressing a charge trapping device, such as a negative differential resistance (NDR) FET is disclosed. By operating/stressing a charge trap device during/after manufacture, a distribution of charge traps can be altered advantageously to improve performance.
Claims20
A method of making a semiconductor device comprising the steps of:
- (a) forming a charge trapping region for the semiconductor device during a first manufacturing operation;
- (b) forming charge traps in said charge trapping region during a sequence of second manufacturing operations, including introducing and distributing impurities within said charge trapping region in a first distribution and a first concentration;
- (c) applying activation energy to the semiconductor device after step (b) is completed to cause a stress current to flow in the semiconductor device, said stress current being adapted to permanently increase said first concentration of charge traps and/or permanently alter said first distribution charge traps in said charge trapping region.
A method of making a negative differential resistance (NDR) transistor device comprising the steps of:
- (a) forming a channel on a substrate for the NDR transistor device;
- and
- (b) forming a charge trapping region proximate to said channel, said charge trapping region including a number of charge trapping sites distributed throughout said charge trapping region;
- wherein said charge trapping sites are configured with a trap concentration and trap distribution so that during normal operation of the semiconductor transistor device a first number of energetic carriers in said channel can be temporarily trapped to provide a negative differential resistance characteristic for the semiconductor transistor device;
- (c) stressing the semiconductor device before it is placed into normal operation so as to increase said first number of energetic carriers in said channel beyond that which would be present during said normal operation;
- wherein said stressing step (c) is used to increase said trap concentration and/or alter said trap distribution in said charge trapping region before the semiconductor transistor device has completed manufacturing operations.
3 more elements
A method of operating a semiconductor transistor device comprising the steps of:
- (a) causing a current to flow in a channel of the semiconductor transistor device;
- and
- (b) trapping energetic carriers from said current in a distribution of charge trapping sites located in a trapping region proximate to said channel;
- wherein said distribution of charge trapping sites are configured so that during normal operation of the semiconductor transistor device it can exhibit a negative differential resistance (NDR) characteristic;
- (c) increasing said concentration of charge trapping sites during normal operation of the semiconductor transistor device to alter said NDR characteristic.
2 more elements
Dependencies are inferred from the claim text.