Write once read only memory employing charge trapping in insulators

A write once read only memory cell, comprising:

• a metal oxide semiconductor field effect transistor (MOSFET) in a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate seperated from the channel region by a gate insulator;
• a wordline coupled to the gate;
• an array plate coupled to the source region;
• a bit line coupled to the drain region;
• and
• wherein the MOSFET is a programmed MOSFET having a charge trapped in the gate insulator adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) adjacent to the drain region and a second voltage threshold region (Vt2) adjacent to the source region, the Vt2 having a greater voltage threshold than Vt1 and such that the programmed MOSFET operates at reduced drain source current.

A memory array, comprising:

• a number of write once read only memory cells, wherein each write once read only memory cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator;
• a number of bit lines coupled to the second source/drain region of each write once read only memory cell along rows of the memory array;
• a number of word lines coupled to the gate of each write once read only memory cell along columns of the memory array;
• an array plate, wherein the first source/drain region of each write once read only memory cell is coupled to the array plate by a conductive plug;
• and
• wherein at least one of write once read only memory cells is a programmed MOSFET having a charge trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed MOSFET operates at reduced drain source current.

A memory device, comprising:

• a memory array, wherein the memory array includes a number of write once read only memory cells, wherein each write once read only memory cell includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator;
• a number of bitlines coupled to the drain region of each write once read only memory cell along rows of the memory array;
• a number of wordlines coupled to the gate of each write once read only memory cell along columns of the memory array;
• an array plate, wherein the source region of each write once read only memory cell is coupled to the array plate by a conductive plug;
• a wordline address decoder coupled to the number of wordlines;
• a bitline address decoder coupled to the number of bitlines;
• a sense amplifier coupled to the number of bitlines;
• and
• wherein at least one of write once read only memory cells is a programmed MOSFET having a charge trapped in the gate insulator adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed MOSFET operates at reduced drain/source current.

An electronic system, comprising:

• a processor;
• and
• a memory device coupled to the processor, wherein the memory device includes;
• a memory array, wherein the memory array includes a number of write once read only memory cells, wherein each write once read only memory cell includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator;
• a number of bitlines coupled to the drain region of each write once read only memory cell along rows of the memory array;
• a number of wordlines coupled to the gate of each write once read only memory cell along columns of the memory array;
• an array plate, wherein the source region of each write once read only memory cell is coupled to the array plate by a conductive plug;
• a wordline address decoder coupled to the number of wordlines;
• a bitline address decoder coupled to the number of bitlines;
• a sense amplifier coupled to the number of bitlines;
• and
• wherein at least one of write once read only memory cells is a programmed MOSFET having a charge trapped in the gate insulator adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2), wherein Vt2 is adjacent the source region of the programmed MOSFET and the programmed MOSFET operates at reduced drain/source current.