Apparatus, methods, and articles of manufacture for a switch having sharpened control voltage
AssigneeMIA-Com, Inc.
InventorsChristopher N. Brindle, Mark F. Kelcourse
Life of this patent
Estimating the term…
Abstract
A sharp control voltage switch utilizing a plurality of field effect transistors (FETs) and a bypass resistance topology to sharpen the control voltage. Utilizing a total of six FETs allows the switch to operate at a low control voltage without the need to increase device periphery or die size. Feed-forward capacitors connected between the gate and source of an uppermost FET and the gate and drain of a lowermost FET are used to reduce signal distortion and improve the linearity and harmonic noise rejection characteristics of the FETs within the switch and thus lower the harmonics of the switch.
Claims52
A switch comprising:
- a plurality of field effect transistors (FETs) connected together in series;
- and
- a bypass resistance topology, including a first terminal and a second terminal, coupled in parallel to said plurality of FETs such that the first terminal is coupled to a first of the plurality of FETs and the second terminal is coupled to a last of the plurality of FETs.
A switch comprising:
- a plurality of field effect transistors (FETs) connected together in series, each FET having a source, a drain and at least one gate, the plurality of FETs having a total of six gates therebetween;
- a bypass resistance topology comprising a single resistor including a first terminal and a second terminal, such that said first terminal is connected to the source of a first FET of said plurality of FETs, and said second terminal is connected to the drain of a last FET of said plurality of FETs;
- a first feed-forward capacitor coupled between the source and the gate of the first FET;
- and
- a second feed-forward capacitor coupled between the drain and the gate of the last FET.
A device having a plurality of switches in parallel to each other and tied to same source voltage input, each switch comprising:
- a plurality of field effect transistors (FETs) connected together in series, said plurality of FETs including an uppermost FET connecting to the source voltage input and a lowermost FET connecting to an output;
- and
- a bypass resistance topology connected to the first FET and the last FET of said plurality of FETs independent of connection to any intervening FETs between the first and last FETs, said bypass resistance topology including a first terminal and a second terminal, said first terminal connected to a source of the first FET of said plurality of FETs, and said second terminal connected to a drain of the last FET of said plurality of FETs.
A method for producing a switch having a sharpened control voltage, the method comprising:
- forming a plurality of field effect transistors (FETs) connected together in series;
- connecting a first FET to a source voltage source;
- connecting each gate to a control voltage source;
- connecting a last FET to an output;
- and
- connecting a resistive element in parallel with the plurality of FETs, said resistive element including a first terminal and a second terminal wherein said first terminal is coupled to the first FET and said second terminal is coupled to the last FET.
A method for sharpening the control voltage of a solid state switch including a plurality of field effect transistors (FETs) connected together in series, the method comprising forming at least one resistive path in parallel with the plurality of FETs so as to provide an alternative current path from a source voltage source to an output, said at least one resistive path including a first end coupled to a first FET of the plurality of FETs, and a second end coupled to a last of the plurality of FETs.
A switch comprising:
- a plurality of field effect transistors (FETs) connected together in series, each FET having a source, a drain and at least one gate, the plurality of FETs having a total of six gates therebetween;
- and
- a bypass resistance topology comprising a single resistor including a first terminal and a second terminal, such that said first terminal is connected to the source of a first FET of said plurality of FETs, and said second terminal is connected to the drain of a last FET of said plurality of FETs.
Dependencies are inferred from the claim text.