Packet prioritization processing technique for routing traffic in a packet-switched computer network

A computer program product for routing traffic in a packet-switched, integrated services network which supports a plurality of different service classes, the network including at least one router, the router including at least one input interface having at least one input interface and at least one output interface, the computer program product comprising:

• a computer usable medium having computer readable code embodied therein, the computer readable code comprising:
• computer code for preprocessing a first packet from said input interface to determine if said first packet is delay sensitive, wherein said preprocessing includes classifying said first packet;
• computer code for storing said first packet in an intermediate data structure before fully processing said first packet in response to a determination that said first packet is not delay sensitive, said intermediate data structure being used for queuing packets which have been preprocessed but which have not yet been processed sufficiently to be routed to an output interface queue;
• computer code for preprocessing a second packet from said input interface while said first packet is queued in said intermediate data structure;
• and
• computer code for fully processing said second packet while said first packet is queued in said intermediate data structure in response to a determination that said second packet is delay sensitive, said fully processing computer code including processing said second packet sufficiently to enable the second packet to be routed to an appropriate output interface queue.

A router for routing traffic in a packet-switched integrated services network which supports a plurality of different service classes, the router comprising:

• a processor;
• at least one input interface;
• at least one output interface;
• and
• memory having at least one intermediate data structure;
• the router being configured or designed to preprocess a first packet from said input interface to determine if said first packet is delay sensitive, wherein said preprocessing includes classifying said first packet;
• the router being configured or designed to store said first packet in an intermediate data structure before fully processing said first packet in response to a determination that said first packet is not delay sensitive, said intermediate data structure being used for queuing packets which have been preprocessed but which have not yet been processed sufficiently to be routed to an output interface queue;
• the router be configured or designed to preprocess a second packet from said input interface while said first packet is queued in said intermediate data structure;
• and
• the router being configured or designed to fully process said second packet, while said first packet is queued in said intermediate data structure, in response to a determination that said second packet is delay sensitive, said fully processing including processing said second packet sufficiently to enable the second packet to be routed to an appropriate output interface queue.

A system for routing traffic in a packet-switched, integrated services network which supports a plurality of different service classes, the network including at least one router, the router including at least one input interface having at least one input interface and at least one output interface, the system comprising:

• means for preprocessing a first packet from said input interface to determine if said first packet is delay sensitive, wherein said preprocessing includes classifying said first packet;
• means for storing said first packet in an intermediate data structure before fully processing said first packet in response to a determination that said first packet is not delay sensitive, said intermediate data structure being used for queuing packets which have been preprocessed but which have not yet been processed sufficiently to be routed to au output interface queue;
• means for preprocessing a second packet from said input interface while said first packet is queued in said intermediate data structure;
• and
• means for fully processing said second packet while said first packet is queued in said intermediate data structure in response to a determination that said second packet is delay sensitive, said fully processing means including processing said second packet sufficiently to enable the second packet to be routed to an appropriate output interface queue.