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US 6,795,359 B1Granted
Methods and apparatus for measuring current as in sensing a memory cell
AssigneeMicron Technology, Inc.
InventorR. Jacob Baker
Life of this patent
Estimating the term…
Abstract
Apparatus and methods sense or measure an input current, such as a current indicating a logic state of a memory cell. A sensing circuit includes an amplifier, a capacitor, a current source circuit, a clocked comparator and a clocked counter. The current source circuit operates responsive to an output of the comparator to supply or withdraw current to and from the capacitor during respective charging and discharging intervals. The count in the clocked counter results from periodic comparisons of the capacitor voltage with a reference voltage and is, therefore, related to the logic state of the memory cell. The magnitude of current supplied during charging is less than the magnitude withdrawn during discharging, allowing use of a smaller counter.
Claims34
A method of measuring an input current comprising:
- receiving the input current at a capacitive element during a sampling period that includes alternating charging and discharging intervals;
- during each charging interval, receiving a positive bias current at the capacitive element until a voltage on the capacitive element exceeds a reference voltage;
- during each discharging interval, receiving a negative bias current at the capacitive element until the capacitive element voltage is less than the reference voltage, the negative bias current's magnitude exceeding the positive bias current's magnitude;
- and
- obtaining a count indicating a proportion of the sampling period during which the capacitor element's voltage exceeds the reference voltage, the count being a measure of the input current.
2 more elements
A method of measuring an input current comprising:
- receiving the input current at a capacitive element during a sampling period that includes alternating charging and discharging intervals, the input current having one of a low value and a high value;
- during each charging interval, receiving a positive bias current at the capacitive element until a voltage on the capacitive element exceeds a reference voltage, the positive bias current being set so that the count is zero for a sampling period in which the input current has the low value and the count is greater than zero for a sampling period in which the input current has the high value;
- during each discharging interval, receiving a negative bias current at the capacitive element until the capacitive element voltage is less than the reference voltage, the negative bias current's magnitude exceeding the positive bias current's magnitude, the average of the magnitudes of the positive and negative bias currents being approximately equal to the low value or the high value;
- and
- obtaining a count indicating a proportion of the sampling period during which the capacitor element's voltage exceeds the reference voltage, the count being a measure of the input current.
2 more elements
A method of sensing a logical state of a memory cell comprising:
- presetting a count value of a counter to a preset count value;
- charging a capacitor with a charging current during a first plurality of time intervals, each time interval of said first plurality terminated when a periodic test of said capacitor indicates that a first voltage thereon exceeds a threshold voltage, the charging current including an input current indicating the memory cell's logical state and a positive bias current;
- discharging said capacitor with a discharging current during a second plurality of time intervals, each time interval of said second plurality terminated when a periodic test of said capacitor indicates that a second voltage thereon is below said threshold voltage, the discharging current including the input current and a negative bias voltage with magnitude greater than the positive bias current;
- and
- periodically incrementing said counter during said first plurality of time intervals and periodically decrementing said counter during said second plurality of time intervals to obtain a net count value, the net count value indicating the logical state of said memory cell.
2 more elements
A sensing circuit for sensing a resistive state of an MRAM memory cell comprising:
- a transconductance amplifier having an input coupled to one end of a resistive element of said MRAM memory cell and an output coupled to a node;
- a capacitor having a first plate coupled to said node and a second plate coupled to a source of constant potential;
- a comparator circuit having a first input coupled to said node, a second input coupled to a first clock signal, a third input coupled to a voltage reference source, a first output and a second output, said second output being in an opposite logical state from said first output;
- a current source having an output coupled to said node, said current source adapted to alternately source or sink a current to said node through said output of said current source, said current source further comprising a first switch and a second switch, wherein said first switch is coupled to said first output of said comparator and said second switch is coupled to said second output of said comparator, said first switch opening or closing in response to said first output of said comparator and said second switch opening or closing in response to said second output of said comparator, and wherein said opening and closing of said first switch and said second switch control whether said current source is sourcing or sinking current at a particular time;
- and
- a counter circuit having a first input coupled to said node, a second input coupled to a second clock signal and an output adapted to output a digital count value.
3 more elements
A sensing circuit for sensing a resistive state of an MRAM memory cell comprising:
- a transconductance amplifier having an input coupled to one end of a resistive element of said MRAM memory cell and an output coupled to a node;
- a capacitor having a first plate coupled to said node and a second plate coupled to a source of constant potential;
- a comparator circuit having a first input coupled to said node, a second input coupled to a first clock signal, a third input coupled to a voltage reference source, a first output and a second output, said second output being in an opposite logical state from said first output;
- a current source having an output coupled to said node, said current source adapted to alternately supply or withdraw current from said capacitor through said output of said current source, said current source further comprising a first switch and a second switch, wherein said first switch is coupled to said first output of said comparator and said second switch is coupled to said second output of said comparator, said first switch opening or closing in response to said first output of said comparator and said second switch opening or closing in response to said second output of said comparator, and wherein said opening and closing of said first switch and said second switch control whether said current source is supplying or withdrawing current at a particular time, wherein said supplying of current is approximately equal to said withdrawing of current plus said output of said transconductance amplifier;
- and
- a counter circuit having a first input coupled to said node, a second input coupled to a second clock signal and an output adapted to output a digital count value.
3 more elements
A sensing circuit for sensing a resistive state of an MRAM memory cell comprising:
- a transconductance amplifier having an input coupled to one end of a resistive element of said MRAM memory cell and an output coupled to a node, said output providing a sensing current;
- a capacitor having a first plate coupled to said node and a second plate coupled to a source of constant potential;
- a comparator circuit having a first input coupled to said node, a second input coupled to a first clock signal, a third input coupled to a voltage reference source, a first output and a second output, said second output being in an opposite logical state from said first output;
- a current source having an output coupled to said node, said current source adapted to alternately supply a positive current or a negative current to said node through said output of said current source, said current source further comprising a first switch and a second switch, wherein said first switch is coupled to said first output of said comparator and said second switch is coupled to said second output of said comparator, said first switch opening or closing in response to said first output of said comparator and said second switch opening or closing in response to said second output of said comparator, and wherein said opening and closing of said first switch and said second switch control whether said sensing current is integrated with said positive current or said negative current at a particular time;
- and
- a counter circuit having a first input coupled to said node, a second input coupled to a second clock signal and an output adapted to output a digital count value.
3 more elements
A sensing circuit comprising:
- input signal circuitry that provides an input current;
- a capacitive element that receives the input current during a sampling period that includes alternating charging and discharging intervals;
- comparison circuitry that provides periodic compare signals indicating whether a voltage on the capacitive element exceeds a reference voltage;
- bias current circuitry that responds to the periodic compare signals by providing a positive bias current during each charging interval until the compare signal indicates the capacitive element's voltage exceeds the reference voltage and by providing a negative bias current during each discharging interval until the compare signal indicates the capacitive clement's voltage is less than the reference voltage, the negative bias current's magnitude exceeding the positive bias current's magnitude;
- and
- count circuitry that responds to the periodic compare signals by providing a count that indicates a proportion of the sampling period during which the capacitive element's voltage exceeds the reference voltage, the count being a measure of the input current.
3 more elements
An integrated circuit comprising:
- a substrate;
- circuitry formed at a surface of the substrate, including:
- an array of resistive memory elements;
- a sensing line extending across the array, connected to a set of resistive memory elements in the array;
- and
- sensing circuitry, including:
- input signal circuitry that provides an input current, the input current indicating a resistance of one of said resistive memory elements connected to the sensing line;
- a capacitive element that receives the input current during a sampling period that includes alternating charging and discharging intervals;
- comparison circuitry that provides periodic compare signals indicating whether a voltage on the capacitive element exceeds a reference voltage;
- bias current circuitry that responds to the periodic compare signals by providing a positive bias current during each charging interval until the compare signal indicates the capacitive element's voltage exceeds the reference voltage and by providing a negative bias current during each discharging interval until the compare signal indicates the capacitive element's voltage is less than the reference voltage, the negative bias current's magnitude exceeding the positive bias current's magnitude;
- and
- count circuitry that responds to the periodic compare signals by providing a count that indicates a proportion of the sampling period during which the capacitive element's voltage exceeds the reference voltage, the count being a measure of the input current.
9 more elements
A digital processing system comprising:
- a processor;
- and
- a resistive memory coupled to said processor via a bus, said resistive memory device including a sensing circuit, said sensing circuit for sensing a resistive state of an MRAM memory cell comprising:
- a transconductance amplifier having an input coupled to one end of a resistive element of said MRAM memory cell and an output coupled to a node;
- a capacitor having a first plate coupled to said node and a second plate coupled to a source of constant potential;
- a comparator circuit having a first input coupled to said node, a second input coupled to a first clock signal, a third input coupled to a voltage reference source, a first output and a second output, said second output being in an opposite logical state from said first output;
- a current source having an output coupled to said node, said current source adapted to alternately source or sink a current to said node through said output of said current source, said current source further comprising a first switch and a second switch, wherein said first switch is coupled to said first output of said comparator and said second switch is coupled to said second output of said comparator, said first switch opening or closing in response to said first output of said comparator and said second switch opening or closing in response to said second output of said comparator, and wherein said opening and closing of said first switch and said second switch control whether said current source is sourcing or sinking current at a particular time;
- and
- a counter circuit having a first input coupled to said node, a second input coupled to a second clock signal and an output adapted to output a digital count value.
6 more elements
A digital processing system comprising:
- a processor;
- and
- a resistive memory coupled to said processor via a bus, said resistive memory device including a sensing circuit, said sensing circuit for sensing a resistive state of an MRAM memory cell comprising:
- a transconductance amplifier having an input coupled to one end of a resistive element of said MRAM memory cell and an output coupled to a node;
- a capacitor having a first plate coupled to said node and a second plate coupled to a source of constant potential;
- a comparator circuit having a first input coupled to said node, a second input coupled to a first clock signal, a third input coupled to a voltage reference source, a first output and a second output, said second output being in an opposite logical state from said first output;
- a current source having an output coupled to said node, said current source adapted to alternately supply or withdraw current from said capacitor through said output of said current source, said current source further comprising a first switch and a second switch, wherein said first switch is coupled to said first output of said comparator and said second switch is coupled to said second output of said comparator, said first switch opening or closing in response to said first output of said comparator and said second switch opening or closing in response to said second output of said comparator, and wherein said opening and closing of said first switch and said second switch control whether said current source is supplying or withdrawing current at a particular time;
- and
- a counter circuit having a first input coupled to said node, a second input coupled to a second clock signal and an output adapted to output a digital count value.
6 more elements
A digital computer system comprising:
- a processor;
- and
- a resistive memory coupled to said processor via a bus, said resistive memory device including a sensing circuit, said sensing circuit for sensing a resistive state of an MRAM memory cell comprising:
- a transconductance amplifier having an input coupled to one end of a resistive element of said MRAM memory cell and an output coupled to a node, said output providing a sensing current;
- a capacitor having a first plate coupled to said node and a second plate coupled to a source of constant potential;
- a comparator circuit having a first input coupled to said node, a second input coupled to a first clock signal, a third input coupled to a voltage reference source, a first output and a second output, said second output being in an opposite logical state from said first output;
- a current source having an output coupled to said node, said current source adapted to alternately supply a positive current or a negative current to said node through said output of said current source, said current source further comprising a first switch and a second switch, wherein said first switch is coupled to said first output of said comparator and said second switch is coupled to said second output of said comparator, said first switch opening or closing in response to said first output of said comparator and said second switch opening or closing in response to said second output of said comparator, and wherein said opening and closing of said first switch and said second switch control whether said sensing current is integrated with said positive current or said negative current at a particular time;
- and
- a counter circuit having a first input coupled to said node, a second input coupled to a second clock signal and an output adapted to output a digital count value.
6 more elements
A digital processing system comprising:
- a processor;
- and
- a resistive memory coupled to said processor via a bus, said resistive memory device including a sensing circuit, said sensing circuit for sensing a resistive state of an MRAM memory cell comprising:
- input signal circuitry that provides an input current;
- a capacitive element that receives the input current during a sampling period that includes alternating charging and discharging intervals;
- comparison circuitry that provides periodic compare signals indicating whether a voltage on the capacitive element exceeds a reference voltage;
- bias current circuitry that responds to the periodic compare signals by providing a positive bias current during each charging interval until the compare signal indicates the capacitive element's voltage exceeds the reference voltage and by providing a negative bias current during each discharging interval until the compare signal indicates the capacitive element's voltage is less than the reference voltage, the negative bias current's magnitude exceeding the positive bias current's magnitude;
- and
- count circuitry that responds to the periodic compare signals by providing a count that indicates a proportion of the sampling period during which the capacitive element's voltage exceeds the reference voltage, the count being a measure of the input current.
6 more elements
Dependencies are inferred from the claim text.